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feat(adc): support ADC calibration on ESP32P4

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This commit is contained in:
gaoxu
2025-01-06 11:04:29 +08:00
parent cfa487b4e0
commit 1b49a1674e
13 changed files with 433 additions and 90 deletions
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10
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -429,7 +429,15 @@ config SOC_ADC_RTC_MAX_BITWIDTH
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default n
default y
config SOC_ADC_SELF_HW_CALI_SUPPORTED
bool
default y
config SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED
bool
default y
config SOC_ADC_SHARED_POWER
bool

92
components/soc/esp32p4/include/soc/regi2c_saradc.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,62 +18,62 @@
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB 0
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_MSB 7
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_LSB 0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB 1
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_MSB 3
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_LSB 0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define I2C_SAR_ADC_ENT_VDD_GRP1 9
#define I2C_SAR_ADC_ENT_VDD_GRP1_MSB 4
#define I2C_SAR_ADC_ENT_VDD_GRP1_LSB 4
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define I2C_SAR_ADC_DTEST_VDD_GRP1 9
#define I2C_SAR_ADC_DTEST_VDD_GRP1_MSB 3
#define I2C_SAR_ADC_DTEST_VDD_GRP1_LSB 0
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_SAMPLE_CYCLE_ADDR 0x5
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 0x3
#define I2C_SARADC_TSENS_DAC_LSB 0x0
#define ADC_SAR2_SAMPLE_CYCLE_ADDR 0x5
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_ENCAL_REF_ADDR 0x7
#define ADC_SAR1_ENCAL_REF_ADDR_MSB 0X4
#define ADC_SAR1_ENCAL_REF_ADDR_LSB 0X4
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x5
#define ADC_SAR1_ENCAL_REF_ADDR 0x7
#define ADC_SAR1_ENCAL_REF_ADDR_MSB 4
#define ADC_SAR1_ENCAL_REF_ADDR_LSB 4
#define ADC_SAR2_ENCAL_REF_ADDR 0x7
#define ADC_SAR2_ENCAL_REF_ADDR_MSB 0x6
#define ADC_SAR2_ENCAL_REF_ADDR_LSB 0x6
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 0x7
#define ADC_SAR2_ENCAL_REF_ADDR 0x7
#define ADC_SAR2_ENCAL_REF_ADDR_MSB 6
#define ADC_SAR2_ENCAL_REF_ADDR_LSB 6
#define I2C_SAR_ADC_DTEST_VDD_GRP1 0x9
#define I2C_SAR_ADC_DTEST_VDD_GRP1_MSB 0x3
#define I2C_SAR_ADC_DTEST_VDD_GRP1_LSB 0x0
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
#define I2C_SAR_ADC_ENT_VDD_GRP1 0x9
#define I2C_SAR_ADC_ENT_VDD_GRP1_MSB 0x4
#define I2C_SAR_ADC_ENT_VDD_GRP1_LSB 0x4

4
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -144,7 +144,9 @@
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (0) /*!< support HW offset calibration version 1*/
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< ADC power control is shared by PWDET, TempSensor */
#define SOC_ADC_SHARED_POWER 1