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Merge branch 'bugfix/bod_glitch_reset_c6_v5.1' into 'release/v5.1'

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bootloader: fix BOD and glitch reset on C6 and H2 (v5.1)

See merge request espressif/esp-idf!23380
This commit is contained in:
morris
2023-04-26 13:09:32 +08:00
parent e1b89eeae0 5c88e0d801
commit 1b6461b9f8
21 changed files with 93 additions and 123 deletions
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2
components/soc/esp32c3/include/soc/rtc_cntl_reg.h
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@@ -2353,7 +2353,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110)