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feat(uhci): add reset and clock control functions
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65
components/hal/esp32/include/hal/uhci_ll.h
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65
components/hal/esp32/include/hal/uhci_ll.h
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/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for UHCI register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#include <stdio.h>
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#include "hal/uhci_types.h"
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#include "soc/uhci_struct.h"
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#include "soc/dport_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enable the bus clock for UHCI module
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*
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* @param group_id Group ID
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* @param enable true to enable, false to disable
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*/
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static inline void _uhci_ll_enable_bus_clock(int group_id, bool enable)
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{
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uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
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if (group_id == 0) {
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reg_val &= ~DPORT_UHCI0_CLK_EN;
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reg_val |= enable << 8;
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} else {
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reg_val &= ~DPORT_UHCI1_CLK_EN;
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reg_val |= enable << 12;
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}
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DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val);
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define uhci_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the UHCI module
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*
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* @param group_id Group ID
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*/
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static inline void _uhci_ll_reset_register(int group_id)
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{
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if (group_id == 0) {
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DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_UHCI0_RST);
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DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
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} else {
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DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_UHCI1_RST);
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DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
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}
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define uhci_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uhci_ll_reset_register(__VA_ARGS__)
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#ifdef __cplusplus
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}
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#endif
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