alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-09 20:41:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

global: bring up esp32s2(not beta)

Browse Source
This commit is contained in:
morris
2019-12-26 15:25:24 +08:00
parent a85b207d68
commit 1c2cc5430e
128 changed files with 17102 additions and 9733 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
components/spi_flash/cache_utils.c
View File

@@ -26,6 +26,8 @@
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/spi_flash.h"
#include "esp32s2beta/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#endif
#include <soc/soc.h>
#include <soc/dport_reg.h>
@@ -36,7 +38,7 @@
#include "esp_spi_flash.h"
#include "esp_log.h"
static __attribute__((unused)) const char* TAG = "cache";
static __attribute__((unused)) const char *TAG = "cache";
#define DPORT_CACHE_BIT(cpuid, regid) DPORT_ ## cpuid ## regid
@@ -51,7 +53,7 @@ static __attribute__((unused)) const char* TAG = "cache";
#define DPORT_CACHE_GET_VAL(cpuid) (cpuid == 0) ? DPORT_CACHE_VAL(PRO) : DPORT_CACHE_VAL(APP)
#define DPORT_CACHE_GET_MASK(cpuid) (cpuid == 0) ? DPORT_CACHE_MASK(PRO) : DPORT_CACHE_MASK(APP)
static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state);
static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
static uint32_t s_flash_op_cache_state[2];
@@ -86,7 +88,7 @@ void spi_flash_op_unlock(void)
when accessing psram from the former CPU.
*/
void IRAM_ATTR spi_flash_op_block_func(void* arg)
void IRAM_ATTR spi_flash_op_block_func(void *arg)
{
// Disable scheduler on this CPU
vTaskSuspendAll();
@@ -136,7 +138,7 @@ void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void)
// Signal to the spi_flash_op_block_task on the other CPU that we need it to
// disable cache there and block other tasks from executing.
s_flash_op_can_start = false;
esp_err_t ret = esp_ipc_call(other_cpuid, &spi_flash_op_block_func, (void*) other_cpuid);
esp_err_t ret = esp_ipc_call(other_cpuid, &spi_flash_op_block_func, (void *) other_cpuid);
assert(ret == ESP_OK);
while (!s_flash_op_can_start) {
// Busy loop and wait for spi_flash_op_block_func to disable cache
@@ -274,7 +276,7 @@ void IRAM_ATTR spi_flash_enable_interrupts_caches_no_os(void)
* function in ROM. They are used to work around a bug where Cache_Read_Disable requires a call to
* Cache_Flush before Cache_Read_Enable, even if cached data was not modified.
*/
static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state)
static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_state)
{
#if CONFIG_IDF_TARGET_ESP32
uint32_t ret = 0;
@@ -298,9 +300,6 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_st
*saved_state = ret;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
*saved_state = Cache_Suspend_ICache();
if (!Cache_Drom0_Using_ICache()) {
*(saved_state + 1) = Cache_Suspend_DCache();
}
#endif
}
@@ -320,9 +319,6 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta
#endif
#elif CONFIG_IDF_TARGET_ESP32S2BETA
Cache_Resume_ICache(saved_state);
if (!Cache_Drom0_Using_ICache()) {
Cache_Resume_DCache(s_flash_op_cache_state[1]);
}
#endif
}
@@ -331,10 +327,7 @@ IRAM_ATTR bool spi_flash_cache_enabled(void)
#if CONFIG_IDF_TARGET_ESP32
bool result = (DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE) != 0);
#elif CONFIG_IDF_TARGET_ESP32S2BETA
bool result = (DPORT_REG_GET_BIT(DPORT_PRO_ICACHE_CTRL_REG, DPORT_PRO_ICACHE_ENABLE) != 0);
if (!Cache_Drom0_Using_ICache()) {
result = result && (DPORT_REG_GET_BIT(DPORT_PRO_DCACHE_CTRL_REG, DPORT_PRO_DCACHE_ENABLE) != 0);
}
bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0);
#endif
#if portNUM_PROCESSORS == 2
result = result && (DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE) != 0);
@@ -356,11 +349,7 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void)
Cache_Allocate_SRAM(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID);
cache_size = CACHE_SIZE_16KB;
#endif
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_4WAYS
cache_ways = CACHE_4WAYS_ASSOC;
#else
cache_ways = CACHE_8WAYS_ASSOC;
#endif
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B
cache_line_size = CACHE_LINE_SIZE_16B;
#elif CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B
@@ -368,7 +357,7 @@ IRAM_ATTR void esp_config_instruction_cache_mode(void)
#else
cache_line_size = CACHE_LINE_SIZE_64B;
#endif
ESP_EARLY_LOGI(TAG, "Instruction cache \t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16,cache_ways == CACHE_4WAYS_ASSOC ? 4: 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
ESP_EARLY_LOGI(TAG, "Instruction cache: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
Cache_Suspend_ICache();
Cache_Set_ICache_Mode(cache_size, cache_ways, cache_line_size);
Cache_Invalidate_ICache_All();
@@ -399,11 +388,7 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
#endif
#endif
#if CONFIG_ESP32S2_DATA_CACHE_4WAYS
cache_ways = CACHE_4WAYS_ASSOC;
#else
cache_ways = CACHE_8WAYS_ASSOC;
#endif
#if CONFIG_ESP32S2_DATA_CACHE_LINE_16B
cache_line_size = CACHE_LINE_SIZE_16B;
#elif CONFIG_ESP32S2_DATA_CACHE_LINE_32B
@@ -411,18 +396,14 @@ IRAM_ATTR void esp_config_data_cache_mode(void)
#else
cache_line_size = CACHE_LINE_SIZE_64B;
#endif
ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, cache_ways == CACHE_4WAYS_ASSOC ? 4: 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
ESP_EARLY_LOGI(TAG, "Data cache \t\t: size %dKB, %dWays, cache line size %dByte", cache_size == CACHE_SIZE_8KB ? 8 : 16, cache_ways == CACHE_4WAYS_ASSOC ? 4 : 8, cache_line_size == CACHE_LINE_SIZE_16B ? 16 : (cache_line_size == CACHE_LINE_SIZE_32B ? 32 : 64));
Cache_Set_DCache_Mode(cache_size, cache_ways, cache_line_size);
Cache_Invalidate_DCache_All();
}
void esp_switch_rodata_to_dcache(void)
{
REG_CLR_BIT(DPORT_PRO_DCACHE_CTRL1_REG, DPORT_PRO_DCACHE_MASK_DROM0);
Cache_Drom0_Source_DCache();
MMU_Drom_ICache_Unmap();
REG_SET_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0);
ESP_EARLY_LOGI(TAG, "Switch rodata load path to data cache.");
}
static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache)
@@ -434,7 +415,11 @@ static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache, bool dcache)
if (dcache) {
d_autoload = Cache_Suspend_DCache();
}
#if CONFIG_IDF_TARGET_ESP32S2BETA
REG_SET_BIT(EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG, EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND);
#else
REG_SET_BIT(DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG, DPORT_PRO_CACHE_FLASH_WRAP_AROUND);
#endif
if (icache) {
Cache_Resume_ICache(i_autoload);
}
@@ -466,11 +451,16 @@ static IRAM_ATTR void esp_enable_cache_spiram_wrap(bool icache, bool dcache)
esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable)
{
int icache_wrap_size = 0, dcache_wrap_size = 0;
int flash_wrap_sizes[2]={-1, -1}, spiram_wrap_sizes[2]={-1, -1};
int flash_wrap_sizes[2] = {-1, -1}, spiram_wrap_sizes[2] = {-1, -1};
int flash_wrap_size = 0, spiram_wrap_size = 0;
int flash_count = 0, spiram_count = 0;
int i;
bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
#if CONFIG_IDF_TARGET_ESP32S2BETA
uint32_t drom0_in_icache = 1;//always 1 in esp32s2
#else
uint32_t drom0_in_icache = Cache_Drom0_Using_ICache();
#endif
if (icache_wrap_enable) {
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B
icache_wrap_size = 16;
@@ -493,11 +483,11 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
uint32_t instruction_use_spiram = 0;
uint32_t rodata_use_spiram = 0;
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
extern uint32_t esp_spiram_instruction_access_enabled();
extern uint32_t esp_spiram_instruction_access_enabled();
instruction_use_spiram = esp_spiram_instruction_access_enabled();
#endif
#if CONFIG_SPIRAM_RODATA
extern uint32_t esp_spiram_rodata_access_enabled();
extern uint32_t esp_spiram_rodata_access_enabled();
rodata_use_spiram = esp_spiram_rodata_access_enabled();
#endif
@@ -507,7 +497,7 @@ extern uint32_t esp_spiram_rodata_access_enabled();
flash_wrap_sizes[0] = icache_wrap_size;
}
if (rodata_use_spiram) {
if (Cache_Drom0_Using_ICache()) {
if (drom0_in_icache) {
spiram_wrap_sizes[0] = icache_wrap_size;
} else {
spiram_wrap_sizes[1] = dcache_wrap_size;
@@ -517,7 +507,7 @@ extern uint32_t esp_spiram_rodata_access_enabled();
spiram_wrap_sizes[1] = dcache_wrap_size;
#endif
} else {
if (Cache_Drom0_Using_ICache()) {
if (drom0_in_icache) {
flash_wrap_sizes[0] = icache_wrap_size;
} else {
flash_wrap_sizes[1] = dcache_wrap_size;
@@ -573,14 +563,14 @@ extern uint32_t esp_spiram_rodata_access_enabled();
return ESP_FAIL;
}
extern bool spi_flash_support_wrap_size(uint32_t wrap_size);
extern bool spi_flash_support_wrap_size(uint32_t wrap_size);
if (!spi_flash_support_wrap_size(flash_wrap_size)) {
flash_support_wrap = false;
ESP_EARLY_LOGW(TAG, "Flash do not support wrap size %d.", flash_wrap_size);
}
#ifdef CONFIG_ESP32S2_SPIRAM_SUPPORT
extern bool psram_support_wrap_size(uint32_t wrap_size);
extern bool psram_support_wrap_size(uint32_t wrap_size);
if (!psram_support_wrap_size(spiram_wrap_size)) {
spiram_support_wrap = false;
ESP_EARLY_LOGW(TAG, "SPIRAM do not support wrap size %d.", spiram_wrap_size);
@@ -592,14 +582,14 @@ extern bool psram_support_wrap_size(uint32_t wrap_size);
return ESP_FAIL;
}
extern esp_err_t spi_flash_enable_wrap(uint32_t wrap_size);
extern esp_err_t spi_flash_enable_wrap(uint32_t wrap_size);
if (flash_support_wrap && flash_wrap_size > 0) {
ESP_EARLY_LOGI(TAG, "Flash wrap enabled.");
spi_flash_enable_wrap(flash_wrap_size);
esp_enable_cache_flash_wrap((flash_wrap_sizes[0] > 0), (flash_wrap_sizes[1] > 0));
}
#if CONFIG_ESP32S2_SPIRAM_SUPPORT
extern esp_err_t psram_enable_wrap(uint32_t wrap_size);
extern esp_err_t psram_enable_wrap(uint32_t wrap_size);
if (spiram_support_wrap && spiram_wrap_size > 0) {
ESP_EARLY_LOGI(TAG, "SPIRAM wrap enabled.");
psram_enable_wrap(spiram_wrap_size);