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https://github.com/espressif/esp-idf.git
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Move panic handler code from FreeRTOS to esp32 component
This commit is contained in:
Jeroen Domburg
273
components/esp32/panic.c
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273
components/esp32/panic.c
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <xtensa/config/core.h>
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#include "rom/rtc.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/xtensa_api.h"
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#include "soc/uart_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timer_group_struct.h"
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#include "gdbstub.h"
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#include "panic.h"
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#define WDT_WRITE_KEY 0x50D83AA1
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/*
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Panic handlers; these get called when an unhandled exception occurs or the assembly-level
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task switching / interrupt code runs into an unrecoverable error. The default task stack
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overflow handler also is in here.
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*/
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#if !CONFIG_FREERTOS_PANIC_SILENT_REBOOT
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//printf may be broken, so we fix our own printing fns...
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inline static void panicPutchar(char c) {
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while (((READ_PERI_REG(UART_STATUS_REG(0))>>UART_TXFIFO_CNT_S)&UART_TXFIFO_CNT)>=126) ;
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WRITE_PERI_REG(UART_FIFO_REG(0), c);
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}
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inline static void panicPutStr(const char *c) {
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int x=0;
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while (c[x]!=0) {
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panicPutchar(c[x]);
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x++;
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}
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}
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inline static void panicPutHex(int a) {
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int x;
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int c;
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panicPutchar(' ');
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for (x=0; x<8; x++) {
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c=(a>>28)&0xf;
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if (c<10) panicPutchar('0'+c); else panicPutchar('a'+c-10);
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a<<=4;
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}
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}
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inline static void panicPutDec(int a) {
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int n1, n2;
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n1=a%10;
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n2=a/10;
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panicPutchar(' ');
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if (n2==0) panicPutchar(' '); else panicPutchar(n2+'0');
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panicPutchar(n1+'0');
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}
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#else
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//No printing wanted. Stub out these functions.
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inline static void panicPutchar(char c) { }
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inline static void panicPutStr(const char *c) { }
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inline static void panicPutHex(int a) { }
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inline static void panicPutDec(int a) { }
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#endif
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void __attribute__((weak)) vApplicationStackOverflowHook( TaskHandle_t xTask, signed char *pcTaskName ) {
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panicPutStr("***ERROR*** A stack overflow in task ");
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panicPutStr((char*)pcTaskName);
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panicPutStr(" has been detected.\r\n");
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}
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static const char *edesc[]={
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"IllegalInstruction", "Syscall", "InstructionFetchError", "LoadStoreError",
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"Level1Interrupt", "Alloca", "IntegerDivideByZero", "PCValue",
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"Privileged", "LoadStoreAlignment", "res", "res",
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"InstrPDAddrError", "LoadStorePIFDataError", "InstrPIFAddrError", "LoadStorePIFAddrError",
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"InstTLBMiss", "InstTLBMultiHit", "InstFetchPrivilege", "res",
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"InstrFetchProhibited", "res", "res", "res",
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"LoadStoreTLBMiss", "LoadStoreTLBMultihit", "LoadStorePrivilege", "res",
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"LoadProhibited", "StoreProhibited", "res", "res",
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"Cp0Dis", "Cp1Dis", "Cp2Dis", "Cp3Dis",
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"Cp4Dis", "Cp5Dis", "Cp6Dis", "Cp7Dis"
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};
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void commonErrorHandler(XtExcFrame *frame);
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//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
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//messing up the serial output, so we kill it here.
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static void haltOtherCore() {
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if (xPortGetCoreID()==0) {
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//Kill app cpu
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CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
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SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
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} else {
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//Kill pro cpu
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CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
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SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
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}
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}
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//Returns true when a debugger is attached using JTAG.
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static int inOCDMode() {
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#if CONFIG_FREERTOS_DEBUG_OCDAWARE
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int dcr;
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int reg=0x10200C; //DSRSET register
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asm("rer %0,%1":"=r"(dcr):"r"(reg));
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return (dcr&0x1);
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#else
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return 0; //Always return no debugger is attached.
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#endif
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}
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void panicHandler(XtExcFrame *frame) {
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int *regs=(int*)frame;
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//Please keep in sync with PANIC_RSN_* defines
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const char *reasons[]={
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"Unknown reason",
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"Unhandled debug exception",
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"Double exception",
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"Unhandled kernel exception",
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"Coprocessor exception",
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"Interrupt wdt timeout on CPU0",
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"Interrupt wdt timeout on CPU1",
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};
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const char *reason=reasons[0];
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//The panic reason is stored in the EXCCAUSE register.
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if (regs[20]<=PANIC_RSN_MAX) reason=reasons[regs[20]];
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haltOtherCore();
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panicPutStr("Guru Meditation Error: Core ");
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panicPutDec(xPortGetCoreID());
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panicPutStr(" panic'ed (");
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panicPutStr(reason);
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panicPutStr(")\r\n");
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if (inOCDMode()) {
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asm("break.n 1");
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}
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commonErrorHandler(frame);
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}
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static void setFirstBreakpoint(uint32_t pc) {
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asm(
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"wsr.ibreaka0 %0\n" \
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"rsr.ibreakenable a3\n" \
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"movi a4,1\n" \
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"or a4, a4, a3\n" \
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"wsr.ibreakenable a4\n" \
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::"r"(pc):"a3","a4");
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}
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void xt_unhandled_exception(XtExcFrame *frame) {
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int *regs=(int*)frame;
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int x;
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haltOtherCore();
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panicPutStr("Guru Meditation Error of type ");
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x=regs[20];
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if (x<40) panicPutStr(edesc[x]); else panicPutStr("Unknown");
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panicPutStr(" occurred on core ");
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panicPutDec(xPortGetCoreID());
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if (inOCDMode()) {
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panicPutStr(" at pc=");
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panicPutHex(regs[1]);
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panicPutStr(". Setting bp and returning..\r\n");
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//Stick a hardware breakpoint on the address the handler returns to. This way, the OCD debugger
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//will kick in exactly at the context the error happened.
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setFirstBreakpoint(regs[1]);
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return;
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}
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panicPutStr(". Exception was unhandled.\r\n");
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commonErrorHandler(frame);
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}
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//Disables all but one WDT, and allows enough time on that WDT to do what we need to do.
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static void reconfigureAllWdts() {
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TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG0.wdt_feed=1;
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TIMERG0.wdt_config0.sys_reset_length=7; //3.2uS
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TIMERG0.wdt_config0.cpu_reset_length=7; //3.2uS
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TIMERG0.wdt_config0.stg0=3; //1st stage timeout: reset system
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TIMERG0.wdt_config1.clk_prescale=80*500; //Prescaler: wdt counts in ticks of 0.5mS
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TIMERG0.wdt_config2=2000; //1 second before reset
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TIMERG0.wdt_config0.en=1;
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TIMERG0.wdt_wprotect=0;
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//Disable wdt 1
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TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG1.wdt_config0.en=0;
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TIMERG1.wdt_wprotect=0;
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}
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static void disableAllWdts() {
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TIMERG0.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG0.wdt_config0.en=0;
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TIMERG0.wdt_wprotect=0;
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TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG1.wdt_config0.en=0;
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TIMERG0.wdt_wprotect=0;
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}
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/*
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We arrive here after a panic or unhandled exception, when no OCD is detected. Dump the registers to the
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serial port and either jump to the gdb stub, halt the CPU or reboot.
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*/
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void commonErrorHandler(XtExcFrame *frame) {
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int *regs=(int*)frame;
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int x, y;
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const char *sdesc[]={
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"PC ","PS ","A0 ","A1 ","A2 ","A3 ","A4 ","A5 ",
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"A6 ","A7 ","A8 ","A9 ","A10 ","A11 ","A12 ","A13 ",
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"A14 ","A15 ","SAR ","EXCCAUSE","EXCVADDR","LBEG ","LEND ","LCOUNT "};
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//Feed the watchdogs, so they will give us time to print out debug info
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reconfigureAllWdts();
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panicPutStr("Register dump:\r\n");
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for (x=0; x<24; x+=4) {
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for (y=0; y<4; y++) {
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if (sdesc[x+y][0]!=0) {
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panicPutStr(sdesc[x+y]);
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panicPutStr(": ");
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panicPutHex(regs[x+y+1]);
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panicPutStr(" ");
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}
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}
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panicPutStr("\r\n");
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}
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#if CONFIG_FREERTOS_PANIC_GDBSTUB
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disableAllWdts();
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panicPutStr("Entering gdb stub now.\r\n");
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gdbstubPanicHandler(frame);
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#elif CONFIG_FREERTOS_PANIC_PRINT_REBOOT || CONFIG_FREERTOS_PANIC_SILENT_REBOOT
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panicPutStr("Rebooting...\r\n");
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for (x=0; x<100; x++) ets_delay_us(1000);
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software_reset();
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#else
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disableAllWdts();
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panicPutStr("CPU halted.\r\n");
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while(1);
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#endif
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}
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void setBreakpointIfJtag(void *fn) {
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if (!inOCDMode()) return;
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setFirstBreakpoint((uint32_t)fn);
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}
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