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spi: fix build fail issue when target is esp32s3

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This commit is contained in:
Armando
2020-09-23 21:01:13 +08:00
parent 4f6fe91c3d
commit 1e1beb69aa
8 changed files with 163 additions and 3 deletions
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22
components/hal/esp32s3/include/hal/spi_ll.h
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@@ -48,6 +48,7 @@ extern "C" {
* stored somewhere to be quickly used.
*/
typedef uint32_t spi_ll_clock_val_t;
typedef spi_dev_t spi_dma_dev_t;
/** IO modes supported by the master. */
typedef enum {
@@ -418,7 +419,7 @@ static inline void spi_ll_master_select_cs(spi_dev_t *hw, int cs_id)
* @param hw Beginning address of the peripheral registers.
* @param val stored clock configuration calculated before (by ``spi_ll_cal_clock``).
*/
static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, spi_ll_clock_val_t *val)
static inline void spi_ll_master_set_clock_by_reg(spi_dev_t *hw, const spi_ll_clock_val_t *val)
{
hw->clock.val = *(uint32_t *)val;
}
@@ -782,6 +783,25 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw)
return 0;
}
static inline void spi_ll_dma_fifo_reset(spi_dev_t *hw)
{
}
static inline void spi_ll_infifo_full_clr(spi_dev_t *hw)
{
}
static inline void spi_ll_dma_rx_enable(spi_dev_t *hw, bool enable)
{
}
static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw)
{
}
static inline void spi_ll_dma_tx_enable(spi_dev_t *hw, bool enable)
{
}
#undef SPI_LL_RST_MASK
#undef SPI_LL_UNUSED_INT_MASK