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feat(adc): support ADC calibration on ESP32C61

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This commit is contained in:
gaoxu
2025-07-10 17:49:05 +08:00
committed by Gao Xu
parent 2e619615de
commit 1e76669a8b
10 changed files with 294 additions and 95 deletions
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12
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
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@@ -263,6 +263,18 @@ config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_CALIBRATION_V1_SUPPORTED
bool
default y
config SOC_ADC_SELF_HW_CALI_SUPPORTED
bool
default y
config SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED
bool
default y
config SOC_ADC_TEMPERATURE_SHARE_INTR
bool
default y

142
components/soc/esp32c61/include/soc/regi2c_saradc.h
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@@ -15,97 +15,97 @@
* function in adc_ll.h.
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define I2C_SAR_ADC 0x69
#define I2C_SAR_ADC_HOSTID 0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 0x3
#define I2C_SARADC_TSENS_DAC_LSB 0x0
#define I2C_SARADC_DTEST 0x7
#define I2C_SARADC_DTEST_MSB 1
#define I2C_SARADC_DTEST_LSB 0
#define I2C_SARADC_DTEST 0x7
#define I2C_SARADC_DTEST_MSB 0x1
#define I2C_SARADC_DTEST_LSB 0x0
#define I2C_SARADC_ENT_TSENS 0x7
#define I2C_SARADC_ENT_TSENS_MSB 2
#define I2C_SARADC_ENT_TSENS_LSB 2
#define I2C_SARADC_ENT_TSENS 0x7
#define I2C_SARADC_ENT_TSENS_MSB 0x2
#define I2C_SARADC_ENT_TSENS_LSB 0x2
#define I2C_SARADC_ENT_SAR 0x7
#define I2C_SARADC_ENT_SAR_MSB 3
#define I2C_SARADC_ENT_SAR_LSB 3
#define I2C_SARADC_ENT_SAR 0x7
#define I2C_SARADC_ENT_SAR_MSB 0x3
#define I2C_SARADC_ENT_SAR_LSB 0x3
#define I2C_SARADC1_ENCAL_REF 0x7
#define I2C_SARADC1_ENCAL_REF_MSB 4
#define I2C_SARADC1_ENCAL_REF_LSB 4
#define I2C_SARADC1_ENCAL_REF 0x7
#define I2C_SARADC1_ENCAL_REF_MSB 0x4
#define I2C_SARADC1_ENCAL_REF_LSB 0x4
#define I2C_SAR1_ENCAL_GND 0x7
#define I2C_SAR1_ENCAL_GND_MSB 5
#define I2C_SAR1_ENCAL_GND_LSB 5
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 0x5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 0x5
#define I2C_SARADC2_ENCAL_REF 0x7
#define I2C_SARADC2_ENCAL_REF_MSB 6
#define I2C_SARADC2_ENCAL_REF_LSB 6
#define I2C_SARADC2_ENCAL_REF 0x7
#define I2C_SARADC2_ENCAL_REF_MSB 0x6
#define I2C_SARADC2_ENCAL_REF_LSB 0x6
#define I2C_SAR2_ENCAL_GND 0x7
#define I2C_SAR2_ENCAL_GND_MSB 7
#define I2C_SAR2_ENCAL_GND_LSB 7
#define I2C_SAR2_ENCAL_GND 0x7
#define I2C_SAR2_ENCAL_GND_MSB 0x7
#define I2C_SAR2_ENCAL_GND_LSB 0x7
#define POWER_GLITCH_XPD_VDET_PERIF 10
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0
#define POWER_GLITCH_XPD_VDET_PERIF 0x10
#define POWER_GLITCH_XPD_VDET_PERIF_MSB 0x0
#define POWER_GLITCH_XPD_VDET_PERIF_LSB 0x0
#define POWER_GLITCH_XPD_VDET_VDDPST 10
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 1
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 1
#define POWER_GLITCH_XPD_VDET_VDDPST 0x10
#define POWER_GLITCH_XPD_VDET_VDDPST_MSB 0x1
#define POWER_GLITCH_XPD_VDET_VDDPST_LSB 0x1
#define POWER_GLITCH_XPD_VDET_PLLBB 10
#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 2
#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 2
#define POWER_GLITCH_XPD_VDET_PLLBB 0x10
#define POWER_GLITCH_XPD_VDET_PLLBB_MSB 0x2
#define POWER_GLITCH_XPD_VDET_PLLBB_LSB 0x2
#define POWER_GLITCH_XPD_VDET_PLL 10
#define POWER_GLITCH_XPD_VDET_PLL_MSB 3
#define POWER_GLITCH_XPD_VDET_PLL_LSB 3
#define POWER_GLITCH_XPD_VDET_PLL 0x10
#define POWER_GLITCH_XPD_VDET_PLL_MSB 0x3
#define POWER_GLITCH_XPD_VDET_PLL_LSB 0x3
#define POWER_GLITCH_DREF_VDET_PERIF 11
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0
#define POWER_GLITCH_DREF_VDET_PERIF 0x11
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 0x2
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0x0
#define POWER_GLITCH_DREF_VDET_VDDPST 11
#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 6
#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 4
#define POWER_GLITCH_DREF_VDET_VDDPST 0x11
#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 0x6
#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 0x4
#define POWER_GLITCH_DREF_VDET_PLLBB 12
#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 2
#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0
#define POWER_GLITCH_DREF_VDET_PLLBB 0x12
#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 0x2
#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0x0
#define POWER_GLITCH_DREF_VDET_PLL 12
#define POWER_GLITCH_DREF_VDET_PLL_MSB 6
#define POWER_GLITCH_DREF_VDET_PLL_LSB 4
#define POWER_GLITCH_DREF_VDET_PLL 0x12
#define POWER_GLITCH_DREF_VDET_PLL_MSB 0x6
#define POWER_GLITCH_DREF_VDET_PLL_LSB 0x4

8
components/soc/esp32c61/include/soc/soc_caps.h
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@@ -104,10 +104,10 @@
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
// /*!< Calibration */ // TODO: [ESP32C61] IDF-9303
// \#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
// \#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
// \#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< Calibration */
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
#define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< Interrupt */
#define SOC_ADC_TEMPERATURE_SHARE_INTR (1)