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update reset reason for c3/s3/h2

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wuzhenghui
2021-08-11 17:35:21 +08:00
committed by Michael (XIAO Xufeng)
parent 673d0371ba
commit 1ef989a1b5
2 changed files with 9 additions and 2 deletions
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3
components/esp_rom/include/esp32s3/rom/rtc.h
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@@ -90,6 +90,9 @@ typedef enum {
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
} RESET_REASON;
typedef enum {