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feat(interrupt): rename interrupt martix reg base

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This commit is contained in:
gaoxu
2024-12-24 19:13:32 +08:00
parent 3e30d2e928
commit 1efea28c69
19 changed files with 242 additions and 242 deletions
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2
components/soc/esp32h2/include/soc/interrupt_reg.h
View File

@@ -21,4 +21,4 @@
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG PLIC_MXINT_CLEAR_REG
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG PLIC_MXINT_TYPE_REG
#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4)
#define DR_REG_INTERRUPT_BASE DR_REG_INTERRUPT_MATRIX_BASE
#define DR_REG_INTERRUPT_BASE DR_REG_INTMTX_BASE

140
components/soc/esp32h2/register/soc/interrupt_matrix_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** INTMTX_CORE0_PMU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0)
/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PMU_INTR mapping register
*/
@@ -26,7 +26,7 @@ extern "C" {
/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4)
/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_EFUSE_INTR mapping register
*/
@@ -38,7 +38,7 @@ extern "C" {
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8)
/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_RTC_TIMER_INTR mapping register
*/
@@ -50,7 +50,7 @@ extern "C" {
/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc)
/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_BLE_TIMER_INTR mapping register
*/
@@ -62,7 +62,7 @@ extern "C" {
/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10)
/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_WDT_INTR mapping register
*/
@@ -74,7 +74,7 @@ extern "C" {
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14)
/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_PERI_TIMEOUT_INTR mapping register
*/
@@ -86,7 +86,7 @@ extern "C" {
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x18)
/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LP_APM_M0_INTR mapping register
*/
@@ -98,7 +98,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x1c)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_0 mapping register
*/
@@ -110,7 +110,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x20)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_1 mapping register
*/
@@ -122,7 +122,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x24)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_2 mapping register
*/
@@ -134,7 +134,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x28)
/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_INTR_FROM_CPU_3 mapping register
*/
@@ -146,7 +146,7 @@ extern "C" {
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c)
/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ASSIST_DEBUG_INTR mapping register
*/
@@ -158,7 +158,7 @@ extern "C" {
/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30)
/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TRACE_INTR mapping register
*/
@@ -170,7 +170,7 @@ extern "C" {
/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34)
/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CACHE_INTR mapping register
*/
@@ -182,7 +182,7 @@ extern "C" {
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38)
/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CPU_PERI_TIMEOUT_INTR mapping register
*/
@@ -194,7 +194,7 @@ extern "C" {
/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c)
/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_MAC_INTR mapping register
*/
@@ -206,7 +206,7 @@ extern "C" {
/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40)
/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_BB_INTR mapping register
*/
@@ -218,7 +218,7 @@ extern "C" {
/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x44)
/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BT_BB_NMI mapping register
*/
@@ -230,7 +230,7 @@ extern "C" {
/** INTMTX_CORE0_COEX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48)
/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_COEX_INTR mapping register
*/
@@ -242,7 +242,7 @@ extern "C" {
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x4c)
/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BLE_TIMER_INTR mapping register
*/
@@ -254,7 +254,7 @@ extern "C" {
/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x50)
/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_BLE_SEC_INTR mapping register
*/
@@ -266,7 +266,7 @@ extern "C" {
/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x54)
/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ZB_MAC_INTR mapping register
*/
@@ -278,7 +278,7 @@ extern "C" {
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x58)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPIO_INTERRUPT_PRO mapping register
*/
@@ -290,7 +290,7 @@ extern "C" {
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x5c)
/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPIO_INTERRUPT_PRO_NMI mapping register
*/
@@ -302,7 +302,7 @@ extern "C" {
/** INTMTX_CORE0_PAU_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x60)
/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PAU_INTR mapping register
*/
@@ -314,7 +314,7 @@ extern "C" {
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x64)
/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_PERI_TIMEOUT_INTR mapping register
*/
@@ -326,7 +326,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68)
/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M0_INTR mapping register
*/
@@ -338,7 +338,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x6c)
/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M1_INTR mapping register
*/
@@ -350,7 +350,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x70)
/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M2_INTR mapping register
*/
@@ -362,7 +362,7 @@ extern "C" {
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74)
/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_HP_APM_M3_INTR mapping register
*/
@@ -374,7 +374,7 @@ extern "C" {
/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x78)
/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_MSPI_INTR mapping register
*/
@@ -386,7 +386,7 @@ extern "C" {
/** INTMTX_CORE0_I2S_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x7c)
/** INTMTX_CORE0_I2S_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2S_INTR mapping register
*/
@@ -398,7 +398,7 @@ extern "C" {
/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80)
/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UHCI0_INTR mapping register
*/
@@ -410,7 +410,7 @@ extern "C" {
/** INTMTX_CORE0_UART0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84)
/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UART0_INTR mapping register
*/
@@ -422,7 +422,7 @@ extern "C" {
/** INTMTX_CORE0_UART1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88)
/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_UART1_INTR mapping register
*/
@@ -434,7 +434,7 @@ extern "C" {
/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c)
/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_LEDC_INTR mapping register
*/
@@ -446,7 +446,7 @@ extern "C" {
/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90)
/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_CAN0_INTR mapping register
*/
@@ -458,7 +458,7 @@ extern "C" {
/** INTMTX_CORE0_USB_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94)
/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_USB_INTR mapping register
*/
@@ -470,7 +470,7 @@ extern "C" {
/** INTMTX_CORE0_RMT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98)
/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_RMT_INTR mapping register
*/
@@ -482,7 +482,7 @@ extern "C" {
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c)
/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2C_EXT0_INTR mapping register
*/
@@ -494,7 +494,7 @@ extern "C" {
/** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0)
/** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_I2C_EXT1_INTR mapping register
*/
@@ -506,7 +506,7 @@ extern "C" {
/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4)
/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG0_T0_INTR mapping register
*/
@@ -518,7 +518,7 @@ extern "C" {
/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8)
/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG0_WDT_INTR mapping register
*/
@@ -530,7 +530,7 @@ extern "C" {
/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac)
/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG1_T0_INTR mapping register
*/
@@ -542,7 +542,7 @@ extern "C" {
/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0)
/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_TG1_WDT_INTR mapping register
*/
@@ -554,7 +554,7 @@ extern "C" {
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4)
/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET0_INTR mapping register
*/
@@ -566,7 +566,7 @@ extern "C" {
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8)
/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET1_INTR mapping register
*/
@@ -578,7 +578,7 @@ extern "C" {
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc)
/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SYSTIMER_TARGET2_INTR mapping register
*/
@@ -590,7 +590,7 @@ extern "C" {
/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0)
/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_APB_ADC_INTR mapping register
*/
@@ -602,7 +602,7 @@ extern "C" {
/** INTMTX_CORE0_PWM_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4)
/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PWM_INTR mapping register
*/
@@ -614,7 +614,7 @@ extern "C" {
/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8)
/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PCNT_INTR mapping register
*/
@@ -626,7 +626,7 @@ extern "C" {
/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc)
/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PARL_IO_TX_INTR mapping register
*/
@@ -638,7 +638,7 @@ extern "C" {
/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0)
/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_PARL_IO_RX_INTR mapping register
*/
@@ -650,7 +650,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4)
/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH0_INTR mapping register
*/
@@ -662,7 +662,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8)
/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH1_INTR mapping register
*/
@@ -674,7 +674,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc)
/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_IN_CH2_INTR mapping register
*/
@@ -686,7 +686,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0)
/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH0_INTR mapping register
*/
@@ -698,7 +698,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4)
/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH1_INTR mapping register
*/
@@ -710,7 +710,7 @@ extern "C" {
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8)
/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_DMA_OUT_CH2_INTR mapping register
*/
@@ -722,7 +722,7 @@ extern "C" {
/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec)
/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_GPSPI2_INTR mapping register
*/
@@ -734,7 +734,7 @@ extern "C" {
/** INTMTX_CORE0_AES_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0)
/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_AES_INTR mapping register
*/
@@ -746,7 +746,7 @@ extern "C" {
/** INTMTX_CORE0_SHA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4)
/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_SHA_INTR mapping register
*/
@@ -758,7 +758,7 @@ extern "C" {
/** INTMTX_CORE0_RSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8)
/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_RSA_INTR mapping register
*/
@@ -770,7 +770,7 @@ extern "C" {
/** INTMTX_CORE0_ECC_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc)
/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ECC_INTR mapping register
*/
@@ -782,7 +782,7 @@ extern "C" {
/** INTMTX_CORE0_ECDSA_INTR_MAP_REG register
* register description
*/
#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100)
/** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
* CORE0_ECDSA_INTR mapping register
*/
@@ -794,7 +794,7 @@ extern "C" {
/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x104)
/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 0~31 mapping register
*/
@@ -806,7 +806,7 @@ extern "C" {
/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x108)
/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 32~63 mapping register
*/
@@ -818,7 +818,7 @@ extern "C" {
/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
* register description
*/
#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x10c)
/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Status register for interrupt sources 64~95 mapping register
*/
@@ -830,7 +830,7 @@ extern "C" {
/** INTMTX_CORE0_CLOCK_GATE_REG register
* register description
*/
#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x110)
/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
* Clock register
*/
@@ -842,7 +842,7 @@ extern "C" {
/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
* register description
*/
#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc)
/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784;
* Version control register
*/

2
components/soc/esp32h2/register/soc/reg_base.h
View File

@@ -20,7 +20,7 @@
#define DR_REG_I2S_BASE 0x6000D000
#define DR_REG_APB_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
#define DR_REG_INTMTX_BASE 0x60010000
#define DR_REG_PCNT_BASE 0x60012000
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_MCPWM_BASE 0x60014000

4
components/soc/esp32h2/system_retention_periph.c
View File

@@ -19,9 +19,9 @@
#include "soc/interrupt_matrix_reg.h"
/* Interrupt Matrix Registers Context */
#define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTERRUPT_MATRIX_BASE) / 4) + 1)
#define N_REGS_INTR_MATRIX() (((INTMTX_CORE0_CLOCK_GATE_REG - DR_REG_INTMTX_BASE) / 4) + 1)
const regdma_entries_config_t intr_matrix_regs_retention[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTERRUPT_MATRIX_BASE, DR_REG_INTERRUPT_MATRIX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_INTMTX_LINK(0), DR_REG_INTMTX_BASE, DR_REG_INTMTX_BASE, N_REGS_INTR_MATRIX(), 0, 0), .owner = ENTRY(0) | ENTRY(2) } /* intr matrix */
};
_Static_assert(ARRAY_SIZE(intr_matrix_regs_retention) == INT_MTX_RETENTION_LINK_LEN, "Inconsistent INT_MTX retention link length definitions");