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Merge branch 'feature/esp32c5mp_light_sleep_support_stage_2' into 'master'

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feat(esp_hw_support): esp32c5mp sleep support (system part)

Closes IDF-8643, PM-195, PM-169, IDF-8641, IDF-8640, IDF-8639, IDF-8638, CV-259, IDF-10308, IDF-10317, IDF-10310, PM-202, IDF-10918, PM-207, PM-208, PM-210, and PM-214

See merge request espressif/esp-idf!31645
This commit is contained in:
Li Shuai
2024-08-29 19:32:05 +08:00
parent 2526ebdaa9 4393343ac9
commit 1fa27cbb0d
128 changed files with 2034 additions and 816 deletions
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48
components/hal/esp32c5/include/hal/lp_aon_ll.h
View File

@@ -110,6 +110,54 @@ static inline void lp_aon_ll_clear_lpcore_etm_wakeup_flag(void)
REG_SET_BIT(LP_AON_LPCORE_REG, LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR);
}
/**
* @brief Set the maximum number of linked lists supported by REGDMA
* @param count: the maximum number of regdma link
*/
static inline void lp_aon_ll_set_regdma_link_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, branch_link_length_aon, count);
}
/**
* @brief Set the maximum number of times a single linked list can run for REGDMA. If a linked list continuously reads in a loop
* for some reason and the execution count exceeds this configured number, a timeout will be triggered.
* @param count: the maximum number of loop
*/
static inline void lp_aon_ll_set_regdma_link_loop_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_work_tout_thres_aon, count);
}
/**
* @brief Set the timeout duration for accessing registers. If REGDMA encounters bus-related issues while accessing
* registers and gets stuck on the bus, a timeout will be triggered.
* @param count: the maximum number of time
*/
static inline void lp_aon_ll_set_regdma_link_reg_access_tout_threshold(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_backup_tout_thres_aon, count);
}
/**
* @brief Set the regdma_link_addr
* @param addr: the addr of regdma_link
*/
static inline void lp_aon_ll_set_regdma_link_addr(uint32_t addr)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg2, link_addr_aon, addr);
}
static inline void lp_aon_ll_set_regdma_link_wait_retry_count(int count)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg1, link_wait_tout_thres_aon, count);
}
static inline void lp_aon_ll_set_regdma_link_wait_read_interval(int interval)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.backup_dma_cfg0, read_interval_aon, interval);
}
#ifdef __cplusplus
}
#endif

73
components/hal/esp32c5/include/hal/pau_ll.h
View File

@@ -34,138 +34,107 @@ static inline void pau_ll_enable_bus_clock(bool enable)
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
return 0;
return dev->regdma_conf.flow_err;
}
static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.link_sel = link;
}
static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.to_mem = to_mem ? 1 : 0;
}
static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.start = 1;
}
static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.start = 0;
}
static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.sel_mac = 1;
}
static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.sel_mac = 0;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.start_mac = 1;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
}
static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
{
HAL_ASSERT(false && "pau not supported yet");
}
static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
{
HAL_ASSERT(false && "pau not supported yet");
}
static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
{
HAL_ASSERT(false && "pau not supported yet");
}
static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
{
HAL_ASSERT(false && "pau not supported yet");
}
static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
{
HAL_ASSERT(false && "pau not supported yet");
dev->regdma_conf.start_mac = 0;
}
static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
return 0;
return dev->regdma_current_link_addr.val;
}
static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
return 0;
return dev->regdma_peri_addr.val;
}
static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
return 0;
return dev->regdma_mem_addr.val;
}
static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
return 0;
return dev->int_raw.val;
}
static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
return 0;
return dev->int_st.val;
}
static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->int_ena.done_int_ena = 1;
}
static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->int_ena.done_int_ena = 0;
}
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->int_ena.error_int_ena = 1;
}
static inline void pau_ll_set_regdma_backup_error_intr_disable(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->int_ena.error_int_ena = 0;
}
static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->int_clr.done_int_clr = 1;
}
static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
{
HAL_ASSERT(false && "pau not supported yet");
dev->int_clr.error_int_clr = 1;
}
#ifdef __cplusplus

4
components/hal/esp32c5/include/hal/pmu_hal.h
View File

@@ -28,6 +28,10 @@ void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);

20
components/hal/esp32c5/include/hal/pmu_ll.h
View File

@@ -637,6 +637,26 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *
return hw->power.wait_timer1.powerup_timer;
}
FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
{
hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle;
}
FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
{
hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
{
hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
{
hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);

1
components/hal/esp32c5/include/hal/timer_ll.h
View File

@@ -24,6 +24,7 @@ extern "C" {
// Get timer group register base address with giving group number
#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
#define TIMER_LL_SLEEP_RETENTION_MODULE_ID(group_id) ((group_id == 0) ? SLEEP_RETENTION_MODULE_TG0_TIMER: SLEEP_RETENTION_MODULE_TG1_TIMER)
#define TIMER_LL_ETM_TASK_TABLE(group, timer, task) \
(uint32_t [2][1][GPTIMER_ETM_TASK_MAX]){{{ \

4
components/hal/esp32c5/include/hal/uart_ll.h
View File

@@ -61,6 +61,10 @@ extern "C" {
#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
// UART sleep retention module
#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
(uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),