esp_system: Reconfigure the WDTs at the start of the panic handler

This is mostly important on ESP32 ECO3 with the
ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core
before we disable the TG1 WDT then the first CPU can get stuck
in WDT ISR handle_livelock_int routine waiting for the other CPU.

components/esp_system/port/panic_handler.c

@@ -50,6 +50,8 @@
 
 extern int _invalid_pc_placeholder;
 
+extern void esp_panic_handler_reconfigure_wdts(void);
+
 extern void esp_panic_handler(panic_info_t *);
 
 static wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
@@ -156,6 +158,9 @@ static void panic_handler(void *frame, bool pseudo_excause)
         }
     }
 
+    // Need to reconfigure WDTs before we stall any other CPU
+    esp_panic_handler_reconfigure_wdts();
+
     esp_rom_delay_us(1);
     SOC_HAL_STALL_OTHER_CORES();
 #endif