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esp32h2: update driver/hal/soc components to support esp32h2

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This commit is contained in:
Shu Chen
2021-06-10 10:28:23 +08:00
parent 983cca8b27
commit 205cd469e9
89 changed files with 7679 additions and 5021 deletions
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49
components/hal/esp32h2/include/hal/adc_ll.h
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@@ -444,7 +444,7 @@ static inline void adc_ll_digi_reset(void)
static inline void adc_ll_pwdet_set_cct(uint32_t cct)
{
/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct;
// RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct; // ESP32H2-TODO
}
/**
@@ -456,7 +456,8 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct)
static inline uint32_t adc_ll_pwdet_get_cct(void)
{
/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
// return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
return 0; // ESP32H2-TODO
}
/**
@@ -684,45 +685,7 @@ static inline void adc_ll_set_calibration_param(adc_ll_num_t adc_n, uint32_t par
*/
static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, bool en)
{
if (en) {
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3);
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2);
SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN);
SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE);
SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE);
APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF;
APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF;
APB_SARADC.onetime_sample.adc1_onetime_sample = 1;
APB_SARADC.onetime_sample.onetime_channel = channel;
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU);
if (adc == ADC_NUM_1) {
/* Config test mux to route v_ref to ADC1 Channels */
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1);
} else {
/* Config test mux to route v_ref to ADC2 Channels */
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
}
} else {
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
APB_SARADC.onetime_sample.adc1_onetime_sample = 0;
APB_SARADC.onetime_sample.onetime_channel = 0xf;
REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0);
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0);
CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN);
CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE);
CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE);
}
// ESP32H2-TODO
}
/*---------------------------------------------------------------
@@ -786,13 +749,13 @@ static inline void adc_ll_onetime_sample_enable(adc_ll_num_t adc_n, bool enable)
static inline uint32_t adc_ll_adc1_read(void)
{
//On ESP32C3, valid data width is 12-bit
//On ESP32H2, valid data width is 12-bit
return (APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff);
}
static inline uint32_t adc_ll_adc2_read(void)
{
//On ESP32C3, valid data width is 12-bit
//On ESP32H2, valid data width is 12-bit
return (APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff);
}

51
components/hal/esp32h2/include/hal/clk_gate_ll.h
View File

@@ -68,18 +68,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return SYSTEM_CRYPTO_HMAC_CLK_EN;
case PERIPH_DS_MODULE:
return SYSTEM_CRYPTO_DS_CLK_EN;
case PERIPH_RNG_MODULE:
return SYSTEM_WIFI_CLK_RNG_EN;
case PERIPH_WIFI_MODULE:
return SYSTEM_WIFI_CLK_WIFI_EN_M;
case PERIPH_BT_MODULE:
return SYSTEM_WIFI_CLK_BT_EN_M;
case PERIPH_WIFI_BT_COMMON_MODULE:
return SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M;
case PERIPH_BT_BASEBAND_MODULE:
return SYSTEM_BT_BASEBAND_EN;
case PERIPH_BT_LC_MODULE:
return SYSTEM_BT_LC_EN;
default:
return 0;
}
@@ -157,14 +145,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
{
switch (periph) {
case PERIPH_RNG_MODULE:
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:
case PERIPH_WIFI_BT_COMMON_MODULE:
case PERIPH_BT_BASEBAND_MODULE:
case PERIPH_BT_LC_MODULE:
return SYSTEM_WIFI_CLK_EN_REG;
case PERIPH_HMAC_MODULE:
case PERIPH_DS_MODULE:
case PERIPH_AES_MODULE:
@@ -180,14 +160,6 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
{
switch (periph) {
case PERIPH_RNG_MODULE:
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:
case PERIPH_WIFI_BT_COMMON_MODULE:
case PERIPH_BT_BASEBAND_MODULE:
case PERIPH_BT_LC_MODULE:
return SYSTEM_WIFI_RST_EN_REG;
case PERIPH_HMAC_MODULE:
case PERIPH_DS_MODULE:
case PERIPH_AES_MODULE:
@@ -212,18 +184,6 @@ static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
}
static inline void IRAM_ATTR periph_ll_wifi_bt_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void IRAM_ATTR periph_ll_wifi_bt_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M);
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_reset(periph_module_t periph)
{
DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
@@ -236,17 +196,6 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
}
static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_wifi_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M);
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
#ifdef __cplusplus
}
#endif

2
components/hal/esp32h2/include/hal/cpu_ll.h
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@@ -69,7 +69,7 @@ static inline void* cpu_ll_get_sp(void)
static inline void cpu_ll_init_hwloop(void)
{
// Nothing needed here for ESP32-C3
// Nothing needed here for ESP32-H2
}
static inline void cpu_ll_set_breakpoint(int id, uint32_t pc)

4
components/hal/esp32h2/include/hal/gpio_ll.h
View File

@@ -18,7 +18,7 @@
* See readme.md in soc/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-C3 GPIO register operations
// The LL layer for ESP32-H2 GPIO register operations
#pragma once
@@ -125,7 +125,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
*/
static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
*status = 0; // Less than 32 GPIOs in ESP32-C3
*status = 0; // Less than 32 GPIOs in ESP32-H2
}
/**

2
components/hal/esp32h2/include/hal/gpspi_flash_ll.h
View File

@@ -34,7 +34,7 @@
extern "C" {
#endif
//NOTE: These macros are changed on c3 for build. MODIFY these when bringup flash.
//NOTE: These macros are changed on h2 for build. MODIFY these when bringup flash.
#define gpspi_flash_ll_get_hw(host_id) ( ((host_id)==SPI2_HOST) ? &GPSPI2 : ({abort();(spi_dev_t*)0;}) )
#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : -1 )

6
components/hal/esp32h2/include/hal/hmac_hal.h
View File

@@ -51,7 +51,7 @@ void hmac_hal_start(void);
* @note Writing out-of-range values is undefined behavior. The user has to ensure that the parameters are in range.
*
* @param config The target of the HMAC. Possible targets are described in \c hmac_hal_output_t.
* See the ESP32C3 TRM for more details.
* See the ESP32H2 TRM for more details.
* @param key_id The ID of the hardware key slot to be used.
*
* @return 0 if the configuration was successful, non-zero if not.
@@ -65,7 +65,7 @@ uint32_t hmac_hal_configure(hmac_hal_output_t config, uint32_t key_id);
*
* The message must not be longer than one block (512 bits) and the padding has to be applied by software before
* writing. The padding has to be able to fit into the block after the message.
* For more information on HMAC padding, see the ESP32C3 TRM.
* For more information on HMAC padding, see the ESP32H2 TRM.
*/
void hmac_hal_write_one_block_512(const void *block);
@@ -80,7 +80,7 @@ void hmac_hal_write_one_block_512(const void *block);
* Before writing the last block which contains the padding, a call to \c hmac_hal_next_block_padding() is necessary
* to indicate to the hardware that a block with padding will be written.
*
* For more information on HMAC padding, see the ESP32C3 TRM.
* For more information on HMAC padding, see the ESP32h2 TRM.
*/
void hmac_hal_write_block_512(const void *block);

2
components/hal/esp32h2/include/hal/hmac_ll.h
View File

@@ -159,7 +159,7 @@ static inline void hmac_ll_msg_padding(void)
* @brief Signals that all blocks have been written and a padding block will automatically be applied by hardware.
*
* Only applies if the message length is a multiple of 512 bits.
* See ESP32C3 TRM HMAC chapter for more details.
* See ESP32H2 TRM HMAC chapter for more details.
*/
static inline void hmac_ll_msg_end(void)
{

134
components/hal/esp32h2/include/hal/i2s_ll.h
View File

@@ -47,7 +47,7 @@ extern "C" {
*/
static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -59,7 +59,7 @@ static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw)
*/
static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -71,7 +71,7 @@ static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw)
*/
static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -83,7 +83,7 @@ static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw)
*/
static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -95,7 +95,7 @@ static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw)
*/
static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -107,7 +107,7 @@ static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw)
*/
static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -119,7 +119,7 @@ static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw)
*/
static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -131,7 +131,7 @@ static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw)
*/
static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -143,7 +143,7 @@ static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw)
*/
static inline void i2s_ll_reset_tx(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -155,7 +155,7 @@ static inline void i2s_ll_reset_tx(i2s_dev_t *hw)
*/
static inline void i2s_ll_reset_rx(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -167,7 +167,7 @@ static inline void i2s_ll_reset_rx(i2s_dev_t *hw)
*/
static inline void i2s_ll_start_out_link(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -178,7 +178,7 @@ static inline void i2s_ll_start_out_link(i2s_dev_t *hw)
*/
static inline void i2s_ll_start_tx(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -189,7 +189,7 @@ static inline void i2s_ll_start_tx(i2s_dev_t *hw)
*/
static inline void i2s_ll_start_in_link(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -200,7 +200,7 @@ static inline void i2s_ll_start_in_link(i2s_dev_t *hw)
*/
static inline void i2s_ll_start_rx(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -211,7 +211,7 @@ static inline void i2s_ll_start_rx(i2s_dev_t *hw)
*/
static inline void i2s_ll_stop_out_link(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -222,7 +222,7 @@ static inline void i2s_ll_stop_out_link(i2s_dev_t *hw)
*/
static inline void i2s_ll_stop_tx(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -233,7 +233,7 @@ static inline void i2s_ll_stop_tx(i2s_dev_t *hw)
*/
static inline void i2s_ll_stop_in_link(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -244,7 +244,7 @@ static inline void i2s_ll_stop_in_link(i2s_dev_t *hw)
*/
static inline void i2s_ll_stop_rx(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -255,7 +255,7 @@ static inline void i2s_ll_stop_rx(i2s_dev_t *hw)
*/
static inline void i2s_ll_enable_dma(i2s_dev_t *hw)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// //Enable and configure DMA
// typeof(hw->lc_conf) lc_conf;
// lc_conf.val = 0;
@@ -271,7 +271,7 @@ static inline void i2s_ll_enable_dma(i2s_dev_t *hw)
*/
static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->int_st.val;
}
@@ -283,7 +283,7 @@ static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -295,7 +295,7 @@ static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->out_eof_des_addr;
}
@@ -307,7 +307,7 @@ static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->in_eof_des_addr;
}
@@ -319,7 +319,7 @@ static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->fifo_conf.tx_fifo_mod;
}
@@ -331,7 +331,7 @@ static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -343,7 +343,7 @@ static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->fifo_conf.rx_fifo_mod;
}
@@ -355,7 +355,7 @@ static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -367,7 +367,7 @@ static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -379,7 +379,7 @@ static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -391,7 +391,7 @@ static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -403,7 +403,7 @@ static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -415,7 +415,7 @@ static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -427,7 +427,7 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->pdm_freq_conf.tx_pdm_fp;
}
@@ -439,7 +439,7 @@ static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->pdm_freq_conf.tx_pdm_fs;
}
@@ -451,7 +451,7 @@ static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -463,7 +463,7 @@ static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -475,7 +475,7 @@ static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->pdm_conf.rx_sinc_dsr_16_en;
}
@@ -487,7 +487,7 @@ static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val)
*/
static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -499,7 +499,7 @@ static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -511,7 +511,7 @@ static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -523,7 +523,7 @@ static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -535,7 +535,7 @@ static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -547,7 +547,7 @@ static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -559,7 +559,7 @@ static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -571,7 +571,7 @@ static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -583,7 +583,7 @@ static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -595,7 +595,7 @@ static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -607,7 +607,7 @@ static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -619,7 +619,7 @@ static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -631,7 +631,7 @@ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -711,7 +711,7 @@ static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw)
*/
static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -723,7 +723,7 @@ static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -735,7 +735,7 @@ static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -747,7 +747,7 @@ static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -759,7 +759,7 @@ static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -771,7 +771,7 @@ static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val)
*/
static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -783,7 +783,7 @@ static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -795,7 +795,7 @@ static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -807,7 +807,7 @@ static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -819,7 +819,7 @@ static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->conf.tx_msb_right;
}
@@ -831,7 +831,7 @@ static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
// *val = hw->conf.rx_msb_right;
}
@@ -843,7 +843,7 @@ static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val)
*/
static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -855,7 +855,7 @@ static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -867,7 +867,7 @@ static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -879,7 +879,7 @@ static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -891,7 +891,7 @@ static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}
@@ -903,7 +903,7 @@ static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val)
{
abort(); // TODO ESP32-C3 IDF-2098
abort(); // TODO ESP32-H2 IDF-2098
}

2
components/hal/esp32h2/include/hal/memprot_ll.h
View File

@@ -29,7 +29,7 @@ extern "C" {
#define IRAM_SRAM_START 0x4037C000
#define DRAM_SRAM_START 0x3FC7C000
/* ICache size is fixed to 16KB on ESP32-C3 */
/* ICache size is fixed to 16KB on ESP32-H2 */
#ifndef ICACHE_SIZE
#define ICACHE_SIZE 0x4000
#endif

2
components/hal/esp32h2/include/hal/mpu_ll.h
View File

@@ -20,7 +20,7 @@
extern "C" {
#endif
/* This LL is currently unused for ESP32-C3 - cleanup is TODO ESP32-C3 IDF-2375 */
/* This LL is currently unused for ESP32-H2 - IDF-2375 */
static inline uint32_t mpu_ll_id_to_addr(unsigned id)
{

9
components/hal/esp32h2/include/hal/rtc_cntl_ll.h
View File

@@ -49,17 +49,12 @@ static inline void rtc_cntl_ll_gpio_clear_wakeup_pins(void)
static inline void rtc_cntl_ll_enable_cpu_retention(uint32_t addr)
{
/* write memory address to register */
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_LINK_ADDR, (uint32_t)addr);
/* Enable clock */
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
/* Enable retention when cpu sleep enable */
REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
// ESP32H2-TODO: IDF-3383
}
static inline void rtc_cntl_ll_disable_cpu_retention(void)
{
REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
// ESP32H2-TODO: IDF-3383
}
#ifdef __cplusplus

6
components/hal/esp32h2/include/hal/spi_ll.h
View File

@@ -27,7 +27,7 @@
#include "hal/hal_defs.h"
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "esp32c3/rom/lldesc.h"
#include "esp32h2/rom/lldesc.h"
#include "esp_attr.h"
#ifdef __cplusplus
@@ -220,7 +220,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
/**
* Reset SPI CPU TX FIFO
*
* On ESP32C3, this function is not seperated
* On ESP32H2, this function is not seperated
*
* @param hw Beginning address of the peripheral registers.
*/
@@ -233,7 +233,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
/**
* Reset SPI CPU RX FIFO
*
* On ESP32C3, this function is not seperated
* On ESP32H2, this function is not seperated
*
* @param hw Beginning address of the peripheral registers.
*/

2
components/hal/esp32h2/include/hal/spimem_flash_ll.h
View File

@@ -126,7 +126,7 @@ static inline void spimem_flash_ll_resume(spi_mem_dev_t *dev)
}
/**
* Initialize auto suspend mode, and esp32c3 doesn't support disable auto-suspend.
* Initialize auto suspend mode, and esp32h2 doesn't support disable auto-suspend.
*
* @param dev Beginning address of the peripheral registers.
* @param auto_sus Enable/disable Flash Auto-Suspend.

4
components/hal/esp32h2/include/hal/timer_ll.h
View File

@@ -362,7 +362,7 @@ static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t tim
*/
static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool edge_int_en)
{
// edge interrupt is not supported on C3
// edge interrupt is not supported on H2
}
/**
@@ -377,7 +377,7 @@ static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t time
*/
static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
{
// edge interrupt is not supported on C3
// edge interrupt is not supported on H2
return false;
}

2
components/hal/esp32h2/include/hal/twai_ll.h
View File

@@ -347,7 +347,7 @@ static inline void twai_ll_set_enabled_intrs(twai_dev_t *hw, uint32_t intr_mask)
* @param triple_sampling Triple Sampling enable/disable
*
* @note Must be called in reset mode
* @note ESP32C3 brp can be any even number between 2 to 32768
* @note ESP32H2 brp can be any even number between 2 to 32768
*/
static inline void twai_ll_set_bus_timing(twai_dev_t *hw, uint32_t brp, uint32_t sjw, uint32_t tseg1, uint32_t tseg2, bool triple_sampling)
{

2
components/hal/esp32h2/include/hal/uhci_types.h
View File

@@ -15,7 +15,7 @@
// Though the UHCI driver hasn't been published, some types are defined here
// for users to develop over the HAL. See example: controller_hci_uart_esp32c3
// for users to develop over the HAL. See example: controller_hci_uart_esp32h2
#pragma once