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esp32h2: update driver/hal/soc components to support esp32h2

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This commit is contained in:
Shu Chen
2021-06-10 10:28:23 +08:00
parent 983cca8b27
commit 205cd469e9
89 changed files with 7679 additions and 5021 deletions
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19
components/soc/esp32h2/gpio_periph.c
View File

@@ -37,6 +37,25 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO19_REG,
IO_MUX_GPIO20_REG,
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,
IO_MUX_GPIO24_REG,
IO_MUX_GPIO25_REG,
IO_MUX_GPIO26_REG,
IO_MUX_GPIO27_REG,
IO_MUX_GPIO28_REG,
IO_MUX_GPIO29_REG,
IO_MUX_GPIO30_REG,
IO_MUX_GPIO31_REG,
IO_MUX_GPIO32_REG,
IO_MUX_GPIO33_REG,
IO_MUX_GPIO34_REG,
IO_MUX_GPIO35_REG,
IO_MUX_GPIO36_REG,
IO_MUX_GPIO37_REG,
IO_MUX_GPIO38_REG,
IO_MUX_GPIO39_REG,
IO_MUX_GPIO40_REG,
};
const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {

2
components/soc/esp32h2/i2s_periph.c
View File

@@ -20,7 +20,7 @@
*/
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
{
// TODO ESP32-C3 IDF-2098
// TODO ESP32-H2 IDF-2098
// .o_bck_in_sig = I2S0O_BCK_IN_IDX,
// .o_ws_in_sig = I2S0O_WS_IN_IDX,

220
components/soc/esp32h2/include/soc/apb_ctrl_reg.h
View File

@@ -19,120 +19,6 @@
extern "C" {
#endif
#include "soc.h"
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000)
/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_RST_TICK_CNT (BIT(12))
#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
#define APB_CTRL_RST_TICK_CNT_V 0x1
#define APB_CTRL_RST_TICK_CNT_S 12
/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_EN (BIT(11))
#define APB_CTRL_CLK_EN_M (BIT(11))
#define APB_CTRL_CLK_EN_V 0x1
#define APB_CTRL_CLK_EN_S 11
/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_320M_EN (BIT(10))
#define APB_CTRL_CLK_320M_EN_M (BIT(10))
#define APB_CTRL_CLK_320M_EN_V 0x1
#define APB_CTRL_CLK_320M_EN_S 10
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: */
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
#define APB_CTRL_PRE_DIV_CNT_S 0
#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004)
/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: */
#define APB_CTRL_TICK_ENABLE (BIT(16))
#define APB_CTRL_TICK_ENABLE_M (BIT(16))
#define APB_CTRL_TICK_ENABLE_V 0x1
#define APB_CTRL_TICK_ENABLE_S 16
/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: */
#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
#define APB_CTRL_CK8M_TICK_NUM_S 8
/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
#define APB_CTRL_XTAL_TICK_NUM_S 0
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008)
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
#define APB_CTRL_CLK_XTAL_OEN_S 10
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
#define APB_CTRL_CLK40X_BB_OEN_V 0x1
#define APB_CTRL_CLK40X_BB_OEN_S 9
/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
#define APB_CTRL_CLK_ADC_INF_OEN_S 7
/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_320M_OEN (BIT(6))
#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
#define APB_CTRL_CLK_320M_OEN_V 0x1
#define APB_CTRL_CLK_320M_OEN_S 6
/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK160_OEN (BIT(5))
#define APB_CTRL_CLK160_OEN_M (BIT(5))
#define APB_CTRL_CLK160_OEN_V 0x1
#define APB_CTRL_CLK160_OEN_S 5
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK80_OEN (BIT(4))
#define APB_CTRL_CLK80_OEN_M (BIT(4))
#define APB_CTRL_CLK80_OEN_V 0x1
#define APB_CTRL_CLK80_OEN_S 4
/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK_BB_OEN (BIT(3))
#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
#define APB_CTRL_CLK_BB_OEN_V 0x1
#define APB_CTRL_CLK_BB_OEN_S 3
/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK44_OEN (BIT(2))
#define APB_CTRL_CLK44_OEN_M (BIT(2))
#define APB_CTRL_CLK44_OEN_V 0x1
#define APB_CTRL_CLK44_OEN_S 2
/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK22_OEN (BIT(1))
#define APB_CTRL_CLK22_OEN_M (BIT(1))
#define APB_CTRL_CLK22_OEN_V 0x1
#define APB_CTRL_CLK22_OEN_S 1
/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define APB_CTRL_CLK20_OEN (BIT(0))
#define APB_CTRL_CLK20_OEN_M (BIT(0))
#define APB_CTRL_CLK20_OEN_V 0x1
#define APB_CTRL_CLK20_OEN_S 0
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C)
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
@@ -149,22 +35,6 @@ extern "C" {
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define APB_CTRL_WIFI_BB_CFG_2_S 0
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014)
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
#define APB_CTRL_WIFI_CLK_EN_S 0
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018)
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
#define APB_CTRL_WIFI_RST_S 0
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C)
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
@@ -386,12 +256,6 @@ extern "C" {
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: */
#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF
#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF
#define APB_CTRL_RETENTION_LINK_ADDR_S 0
#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
@@ -480,30 +344,68 @@ extern "C" {
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4
/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
/* APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000003
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3))
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_V 0x1
#define APB_CTRL_PERI_BACKUP_ADDR_MAP_MODE_S 3
/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000007
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x3
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 1
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x7
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 0
#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B8)
/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/* APB_CTRL_PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define APB_CTRL_BACKUP_APB_START_ADDR_M ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
#define APB_CTRL_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_BACKUP_APB_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_M ((APB_CTRL_PERI_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_APB_START_ADDR_S))
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_APB_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC)
/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/* APB_CTRL_PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define APB_CTRL_BACKUP_MEM_START_ADDR_M ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
#define APB_CTRL_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_BACKUP_MEM_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_M ((APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S))
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MEM_START_ADDR_S 0
#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0C0)
#define APB_CTRL_PERI_BACKUP_MAP0_REG (DR_REG_APB_CTRL_BASE + 0x0C0)
/* APB_CTRL_PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP0 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP0_M ((APB_CTRL_PERI_BACKUP_MAP0_V)<<(APB_CTRL_PERI_BACKUP_MAP0_S))
#define APB_CTRL_PERI_BACKUP_MAP0_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP0_S 0
#define APB_CTRL_PERI_BACKUP_MAP1_REG (DR_REG_APB_CTRL_BASE + 0x0C4)
/* APB_CTRL_PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP1 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP1_M ((APB_CTRL_PERI_BACKUP_MAP1_V)<<(APB_CTRL_PERI_BACKUP_MAP1_S))
#define APB_CTRL_PERI_BACKUP_MAP1_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP1_S 0
#define APB_CTRL_PERI_BACKUP_MAP2_REG (DR_REG_APB_CTRL_BASE + 0x0C8)
/* APB_CTRL_PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP2 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP2_M ((APB_CTRL_PERI_BACKUP_MAP2_V)<<(APB_CTRL_PERI_BACKUP_MAP2_S))
#define APB_CTRL_PERI_BACKUP_MAP2_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP2_S 0
#define APB_CTRL_PERI_BACKUP_MAP3_REG (DR_REG_APB_CTRL_BASE + 0x0CC)
/* APB_CTRL_PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_MAP3 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP3_M ((APB_CTRL_PERI_BACKUP_MAP3_V)<<(APB_CTRL_PERI_BACKUP_MAP3_S))
#define APB_CTRL_PERI_BACKUP_MAP3_V 0xFFFFFFFF
#define APB_CTRL_PERI_BACKUP_MAP3_S 0
#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0D0)
/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1))
@@ -517,7 +419,7 @@ extern "C" {
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0
#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0C4)
#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0D4)
/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1))
@@ -531,7 +433,7 @@ extern "C" {
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0
#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0C8)
#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0D8)
/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1))
@@ -545,7 +447,7 @@ extern "C" {
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0
#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0D0)
#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0DC)
/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1))
@@ -559,8 +461,16 @@ extern "C" {
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0
#define APB_CTRL_CLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0E0)
/* APB_CTRL_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define APB_CTRL_CLK_EN (BIT(0))
#define APB_CTRL_CLK_EN_M (BIT(0))
#define APB_CTRL_CLK_EN_V 0x1
#define APB_CTRL_CLK_EN_S 0
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101050 ; */
/*description: Version control*/
#define APB_CTRL_DATE 0xFFFFFFFF
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))

100
components/soc/esp32h2/include/soc/apb_ctrl_struct.h
View File

@@ -18,46 +18,13 @@ extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t pre_div: 10;
uint32_t clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t rst_tick: 1;
uint32_t reserved13: 19;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t xtal_tick: 8;
uint32_t ck8m_tick: 8;
uint32_t tick_enable: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
uint32_t clk22_oen: 1;
uint32_t clk44_oen: 1;
uint32_t clk_bb_oen: 1;
uint32_t clk80_oen: 1;
uint32_t clk160_oen: 1;
uint32_t clk_320m_oen: 1;
uint32_t clk_adc_inf_oen: 1;
uint32_t clk_dac_cpu_oen: 1;
uint32_t clk40x_bb_oen: 1;
uint32_t clk_xtal_oen: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} clk_out_en;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t reserved_14;
uint32_t reserved_18;
union {
struct {
uint32_t peri_io_swap: 8;
@@ -101,10 +68,10 @@ typedef volatile struct {
};
uint32_t val;
} flash_ace3_attr;
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
uint32_t flash_ace0_addr; /**/
uint32_t flash_ace1_addr; /**/
uint32_t flash_ace2_addr; /**/
uint32_t flash_ace3_addr; /**/
union {
struct {
uint32_t flash_ace0_size:13;
@@ -154,7 +121,7 @@ typedef volatile struct {
};
uint32_t val;
} spi_mem_pms_ctrl;
uint32_t spi_mem_reject_addr; /**/
uint32_t spi_mem_reject_addr; /**/
union {
struct {
uint32_t sdio_win_access_en: 1;
@@ -190,7 +157,7 @@ typedef volatile struct {
} front_end_mem_pd;
union {
struct {
uint32_t retention_link_addr: 27;
uint32_t reserved0: 27;
uint32_t nobypass_cpu_iso_rst: 1;
uint32_t reserved28: 4;
};
@@ -220,23 +187,26 @@ typedef volatile struct {
};
uint32_t val;
} mem_power_up;
uint32_t rnd_data; /**/
uint32_t rnd_data; /**/
union {
struct {
uint32_t reserved0: 1;
uint32_t peri_backup_flow_err: 2;
uint32_t reserved3: 1;
uint32_t peri_backup_burst_limit: 5;
uint32_t peri_backup_tout_thres: 10;
uint32_t peri_backup_size: 10;
uint32_t peri_backup_start: 1;
uint32_t peri_backup_to_mem: 1;
uint32_t peri_backup_ena: 1;
uint32_t peri_backup_flow_err: 3;
uint32_t peri_backup_addr_map_mode: 1;
uint32_t peri_backup_burst_limit: 5;
uint32_t peri_backup_tout_thres: 10;
uint32_t peri_backup_size: 10;
uint32_t peri_backup_start: 1;
uint32_t peri_backup_to_mem: 1;
uint32_t peri_backup_ena: 1;
};
uint32_t val;
} peri_backup_config;
uint32_t peri_backup_addr; /**/
uint32_t peri_backup_mem_addr; /**/
uint32_t peri_backup_addr; /**/
uint32_t peri_backup_mem_addr; /**/
uint32_t peri_backup_map0; /**/
uint32_t peri_backup_map1; /**/
uint32_t peri_backup_map2; /**/
uint32_t peri_backup_map3; /**/
union {
struct {
uint32_t peri_backup_done: 1;
@@ -261,7 +231,6 @@ typedef volatile struct {
};
uint32_t val;
} peri_backup_int_ena;
uint32_t reserved_cc;
union {
struct {
uint32_t peri_backup_done: 1;
@@ -270,10 +239,13 @@ typedef volatile struct {
};
uint32_t val;
} peri_backup_int_clr;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} ctrlclk_conf;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
@@ -472,7 +444,7 @@ typedef volatile struct {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t date; /*Version control*/
uint32_t date; /*Version control*/
} apb_ctrl_dev_t;
extern apb_ctrl_dev_t APB_CTRL;
#ifdef __cplusplus

21
components/soc/esp32h2/include/soc/apb_saradc_reg.h
View File

@@ -204,6 +204,12 @@ extern "C" {
#define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
#define APB_SARADC_ONETIME_ATTEN_V 0x3
#define APB_SARADC_ONETIME_ATTEN_S 23
/* APB_SARADC_ONETIME_EN_TEST : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_ONETIME_EN_TEST (BIT(22))
#define APB_SARADC_ONETIME_EN_TEST_M (BIT(22))
#define APB_SARADC_ONETIME_EN_TEST_V 0x1
#define APB_SARADC_ONETIME_EN_TEST_S 22
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024)
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
@@ -344,6 +350,19 @@ extern "C" {
#define APB_SARADC_THRES1_EN_M (BIT(30))
#define APB_SARADC_THRES1_EN_V 0x1
#define APB_SARADC_THRES1_EN_S 30
/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_THRES2_EN (BIT(29))
#define APB_SARADC_THRES2_EN_M (BIT(29))
#define APB_SARADC_THRES2_EN_V 0x1
#define APB_SARADC_THRES2_EN_S 29
/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define APB_SARADC_THRES3_EN (BIT(28))
#define APB_SARADC_THRES3_EN_M (BIT(28))
#define APB_SARADC_THRES3_EN_V 0x1
#define APB_SARADC_THRES3_EN_S 28
/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
/*description: */
#define APB_SARADC_THRES_ALL_EN (BIT(27))
#define APB_SARADC_THRES_ALL_EN_M (BIT(27))
@@ -615,7 +634,7 @@ extern "C" {
#define APB_SARADC_CALI_CFG_S 0
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */
/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02102260 ; */
/*description: */
#define APB_SARADC_DATE 0xFFFFFFFF
#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))

6
components/soc/esp32h2/include/soc/apb_saradc_struct.h
View File

@@ -76,7 +76,8 @@ typedef volatile struct {
} sar_patt_tab[2];
union {
struct {
uint32_t reserved0: 23;
uint32_t reserved0: 22;
uint32_t onetime_en_test: 1;
uint32_t onetime_atten: 2;
uint32_t onetime_channel: 4;
uint32_t onetime_start: 1;
@@ -148,7 +149,8 @@ typedef volatile struct {
struct {
uint32_t reserved0: 27;
uint32_t thres_all_en: 1;
uint32_t reserved28: 2;
uint32_t thres3_en: 1;
uint32_t thres2_en: 1;
uint32_t thres1_en: 1;
uint32_t thres0_en: 1;
};

1056
components/soc/esp32h2/include/soc/clkrst_reg.h Normal file
View File

File diff suppressed because it is too large Load Diff

2
components/soc/esp32h2/include/soc/dport_access.h
View File

@@ -18,7 +18,7 @@
#include <stdint.h>
#include "esp_attr.h"
#include "esp_attr.h"
#include "esp32c3/dport_access.h"
#include "esp32h2/dport_access.h"
#include "soc.h"
#include "uart_reg.h"

2
components/soc/esp32h2/include/soc/efuse_reg.h
View File

@@ -767,7 +767,7 @@ extern "C" {
#define EFUSE_SYS_DATA_PART0_0_V 0xFF
#define EFUSE_SYS_DATA_PART0_0_S 25
/* EFUSE_PKG_VERSION : RO ;bitpos:[23:21] ;default: 3'h0 ; */
/*description: Package version 0:ESP32-C3 */
/*description: Package version 0:ESP32-H2 */
#define EFUSE_PKG_VERSION 0x00000007
#define EFUSE_PKG_VERSION_M ((EFUSE_PKG_VERSION_V)<<(EFUSE_PKG_VERSION_S))
#define EFUSE_PKG_VERSION_V 0x7

4350
components/soc/esp32h2/include/soc/gpio_reg.h
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File diff suppressed because it is too large Load Diff

92
components/soc/esp32h2/include/soc/gpio_sig_map.h
View File

@@ -49,30 +49,38 @@
#define I2SI_BCK_OUT_IDX 16
#define I2SI_WS_IN_IDX 17
#define I2SI_WS_OUT_IDX 17
#define GPIO_BT_PRIORITY_IDX 18
#define GPIO_WLAN_PRIO_IDX 18
#define GPIO_BT_ACTIVE_IDX 19
#define GPIO_WLAN_ACTIVE_IDX 19
#define BB_DIAG0_IDX 20
#define BB_DIAG1_IDX 21
#define BB_DIAG2_IDX 22
#define BB_DIAG3_IDX 23
#define BB_DIAG4_IDX 24
#define BB_DIAG5_IDX 25
#define BB_DIAG6_IDX 26
#define BB_DIAG7_IDX 27
#define BB_DIAG8_IDX 28
#define BB_DIAG9_IDX 29
#define BB_DIAG10_IDX 30
#define BB_DIAG11_IDX 31
#define BB_DIAG12_IDX 32
#define BB_DIAG13_IDX 33
#define BB_DIAG14_IDX 34
#define BB_DIAG15_IDX 35
#define BB_DIAG16_IDX 36
#define BB_DIAG17_IDX 37
#define BB_DIAG18_IDX 38
#define BB_DIAG19_IDX 39
#define CO_EXT_PRIORITY_IN_IDX 18
#define I2SO_SD1_OUT_IDX 18
#define CO_EXT_ACTIVE_IN_IDX 19
#define CO_EXT_ACTIVE_OUT_IDX 19
#define CPU_TESTBUS0_IDX 20
#define CPU_TESTBUS1_IDX 21
#define CPU_TESTBUS2_IDX 22
#define CPU_TESTBUS3_IDX 23
#define CPU_TESTBUS4_IDX 24
#define CPU_TESTBUS5_IDX 25
#define CPU_TESTBUS6_IDX 26
#define CPU_TESTBUS7_IDX 27
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define USB_JTAG_TCK_IDX 36
#define USB_JTAG_TMS_IDX 37
#define USB_JTAG_TDI_IDX 38
#define USB_JTAG_TDO_IDX 39
#define USB_EXTPHY_VP_IDX 40
#define USB_EXTPHY_OEN_IDX 40
#define USB_EXTPHY_VM_IDX 41
@@ -100,6 +108,14 @@
#define GPIO_SD1_OUT_IDX 56
#define GPIO_SD2_OUT_IDX 57
#define GPIO_SD3_OUT_IDX 58
#define EVENT_MATRIX_IN0_IDX 59
#define TASK_MATRIX_OUT0_IDX 59
#define EVENT_MATRIX_IN1_IDX 60
#define TASK_MATRIX_OUT1_IDX 60
#define EVENT_MATRIX_IN2_IDX 61
#define TASK_MATRIX_OUT2_IDX 61
#define EVENT_MATRIX_IN3_IDX 62
#define TASK_MATRIX_OUT3_IDX 62
#define FSPICLK_IN_IDX 63
#define FSPICLK_OUT_IDX 63
#define FSPIQ_IN_IDX 64
@@ -155,30 +171,26 @@
#define SIG_IN_FUNC100_IDX 100
#define SYNCERR_IDX 101
#define SYNCFOUND_FLAG_IDX 102
#define EVT_CNTL_IMMEDIATE_ABORT_IDX 103
#define LINKLBL_IDX 104
#define CH_IDX_IDX 103
#define RX_WINDOW_IDX 104
#define DATA_EN_IDX 105
#define DATA_IDX 106
#define PKT_TX_ON_IDX 107
#define PKT_RX_ON_IDX 108
#define RW_TX_ON_IDX 109
#define RW_RX_ON_IDX 110
#define EVT_REQ_P_IDX 111
#define EVT_STOP_P_IDX 112
#define BT_MODE_ON_IDX 113
#define GPIO_LC_DIAG0_IDX 114
#define GPIO_LC_DIAG1_IDX 115
#define GPIO_LC_DIAG2_IDX 116
#define CH_IDX_IDX 117
#define RX_WINDOW_IDX 118
#define UPDATE_RX_IDX 119
#define RX_STATUS_IDX 120
#define CLK_GPIO_IDX 121
#define NBT_BLE_IDX 122
#define TXRU_ON_IDX 109
#define RXRU_ON_IDX 110
#define LELC_ST3_IDX 111
#define LELC_ST2_IDX 112
#define LELC_ST1_IDX 113
#define LELC_ST0_IDX 114
#define CRCOK_IDX 115
#define CLK_GPIO_IDX 116
#define RADIO_START_IDX 117
#define CLK_OUT_OUT1_IDX 123
#define CLK_OUT_OUT2_IDX 124
#define CLK_OUT_OUT3_IDX 125
#define SPICS1_OUT_IDX 126
#define USB_JTAG_TRST_IDX 127
#define SIG_GPIO_OUT_IDX 128
#define GPIO_MAP_DATE_IDX 0x2006130
#endif /* _SOC_GPIO_SIG_MAP_H_ */

22
components/soc/esp32h2/include/soc/i2s_caps.h Normal file
View File

@@ -0,0 +1,22 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
#define SOC_I2S_NUM (1)

33
components/soc/esp32h2/include/soc/i2s_reg.h
View File

@@ -124,6 +124,18 @@ extern "C" {
#define I2S_RX_DONE_INT_CLR_S 0
#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020)
/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
/*description: */
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(22))
#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(22))
#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1
#define I2S_RX_PDM_SINC_DSR_16_EN_S 22
/* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
/*description: 1: Enable PDM2PCM RX mode. 0: DIsable.*/
#define I2S_RX_PDM2PCM_EN (BIT(21))
#define I2S_RX_PDM2PCM_EN_M (BIT(21))
#define I2S_RX_PDM2PCM_EN_V 0x1
#define I2S_RX_PDM2PCM_EN_S 21
/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/
#define I2S_RX_PDM_EN (BIT(20))
@@ -935,6 +947,27 @@ T12_5[2:0]).*/
#define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S))
#define I2S_RX_WS_OUT_DM_V 0x3
#define I2S_RX_WS_OUT_DM_S 16
/* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay
by pos edge. 2: delay by neg edge. 3: not used.*/
#define I2S_RX_SD3_IN_DM 0x00000003
#define I2S_RX_SD3_IN_DM_M ((I2S_RX_SD3_IN_DM_V)<<(I2S_RX_SD3_IN_DM_S))
#define I2S_RX_SD3_IN_DM_V 0x3
#define I2S_RX_SD3_IN_DM_S 12
/* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay
by pos edge. 2: delay by neg edge. 3: not used.*/
#define I2S_RX_SD2_IN_DM 0x00000003
#define I2S_RX_SD2_IN_DM_M ((I2S_RX_SD2_IN_DM_V)<<(I2S_RX_SD2_IN_DM_S))
#define I2S_RX_SD2_IN_DM_V 0x3
#define I2S_RX_SD2_IN_DM_S 8
/* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay
by pos edge. 2: delay by neg edge. 3: not used.*/
#define I2S_RX_SD1_IN_DM 0x00000003
#define I2S_RX_SD1_IN_DM_M ((I2S_RX_SD1_IN_DM_V)<<(I2S_RX_SD1_IN_DM_S))
#define I2S_RX_SD1_IN_DM_V 0x3
#define I2S_RX_SD1_IN_DM_S 4
/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay
by pos edge. 2: delay by neg edge. 3: not used.*/

38
components/soc/esp32h2/include/soc/i2s_struct.h
View File

@@ -83,7 +83,9 @@ typedef volatile struct {
uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/
uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
uint32_t reserved23: 11; /*Reserve*/
uint32_t rx_pdm2pcm_en: 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
uint32_t rx_sinc_dsr_16_en: 1;
uint32_t reserved23: 9; /*Reserve*/
};
uint32_t val;
} rx_conf;
@@ -136,8 +138,7 @@ typedef volatile struct {
uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/
uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
uint32_t tx_bck_no_dly: 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
uint32_t reserved31: 1; /* Reserved*/
uint32_t reserved30: 2; /*Reserved*/
};
uint32_t val;
} tx_conf1;
@@ -263,7 +264,13 @@ typedef volatile struct {
union {
struct {
uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2 : 14; /* Reserved*/
uint32_t reserved2: 2;
uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6: 2;
uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved10: 2;
uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved14: 2;
uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2;
uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
@@ -277,18 +284,16 @@ typedef volatile struct {
} rx_timing;
union {
struct {
uint32_t tx_sd_out_dm : 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2 : 2; /* Reserved*/
uint32_t tx_sd1_out_dm : 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6 : 10; /* Reserved*/
uint32_t tx_ws_out_dm : 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18 : 2; /* Reserved*/
uint32_t tx_bck_out_dm : 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22 : 2; /* Reserved*/
uint32_t tx_ws_in_dm : 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26 : 2; /* Reserved*/
uint32_t tx_bck_in_dm : 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30 : 2; /* Reserved*/
uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved2: 14; /*Reserved*/
uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved18: 2;
uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2;
uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved26: 2;
uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30: 2;
};
uint32_t val;
} tx_timing;
@@ -329,6 +334,7 @@ typedef volatile struct {
} date;
} i2s_dev_t;
extern i2s_dev_t I2S0;
#ifdef __cplusplus
}
#endif

147
components/soc/esp32h2/include/soc/interrupt_core0_reg.h
View File

@@ -518,7 +518,63 @@ extern "C" {
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
/* INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_TG3_T0_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M ((INTERRUPT_CORE0_TG3_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_T0_INT_MAP_S))
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG3_T0_INT_MAP_S 0
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
/* INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG3_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_WDT_INT_MAP_S))
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_S 0
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S))
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S 0
#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
/* INTERRUPT_CORE0_IEEE802154MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_M ((INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V)<<(INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S))
#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S 0
#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
/* INTERRUPT_CORE0_IEEE802154BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_M ((INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V)<<(INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S))
#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S 0
#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_COEX_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_COEX_INT_MAP_M ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S))
#define INTERRUPT_CORE0_COEX_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_COEX_INT_MAP_S 0
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/* INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
/*description: */
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP 0x0000001F
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M ((INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V)<<(INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S))
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V 0x1F
#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S 0
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF
@@ -526,7 +582,7 @@ extern "C" {
#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_0_S 0
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF
@@ -534,7 +590,15 @@ extern "C" {
#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_1_S 0
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF
#define INTERRUPT_CORE0_INTR_STATUS_2_S 0
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define INTERRUPT_CORE0_CLK_EN (BIT(0))
@@ -542,7 +606,7 @@ extern "C" {
#define INTERRUPT_CORE0_CLK_EN_V 0x1
#define INTERRUPT_CORE0_CLK_EN_S 0
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF
@@ -550,7 +614,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF
@@ -558,7 +622,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF
@@ -566,7 +630,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF
@@ -574,7 +638,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F
@@ -582,7 +646,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F
@@ -590,7 +654,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F
@@ -598,7 +662,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F
@@ -606,7 +670,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F
@@ -614,7 +678,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F
@@ -622,7 +686,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F
@@ -630,7 +694,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F
@@ -638,7 +702,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F
@@ -646,7 +710,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F
@@ -654,7 +718,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F
@@ -662,7 +726,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F
@@ -670,7 +734,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F
@@ -678,7 +742,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F
@@ -686,7 +750,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F
@@ -694,7 +758,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F
@@ -702,7 +766,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F
@@ -710,7 +774,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F
@@ -718,7 +782,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F
@@ -726,7 +790,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F
@@ -734,7 +798,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F
@@ -742,7 +806,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F
@@ -750,7 +814,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F
@@ -758,7 +822,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F
@@ -766,7 +830,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F
@@ -774,7 +838,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F
@@ -782,7 +846,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19C)
/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F
@@ -790,7 +854,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0)
/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F
@@ -798,7 +862,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4)
/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F
@@ -806,7 +870,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8)
/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F
@@ -814,7 +878,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC)
/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F
@@ -822,7 +886,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0
#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0)
/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F
@@ -831,7 +895,7 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0
#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4)
/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
/*description: */
#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F
@@ -840,13 +904,14 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007210 ; */
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2011090 ; */
/*description: */
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF
#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF
#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
#ifdef __cplusplus
}
#endif

102
components/soc/esp32h2/include/soc/io_mux_reg.h
View File

@@ -116,6 +116,30 @@
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_GPIO22_U
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_GPIO23_U
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_GPIO25_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_GPIO26_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_GPIO27_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_GPIO28_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_GPIO30_U
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_GPIO31_U
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_GPIO32_U
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_GPIO39_U
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_GPIO40_U
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_GPIO41_U
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_GPIO42_U
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_GPIO43_U
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_GPIO44_U
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
/* Value to set in IO Mux to use a pin as GPIO. */
#define PIN_FUNC_GPIO 1
@@ -266,9 +290,85 @@
#define FUNC_U0TXD_GPIO21 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO22_U (REG_IO_MUX_BASE +0x5c)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_GPIO23_U (REG_IO_MUX_BASE +0x60)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE +0x64)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
#define PERIPHS_IO_MUX_GPIO25_U (REG_IO_MUX_BASE +0x68)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_GPIO26_U (REG_IO_MUX_BASE +0x6c)
#define FUNC_GPIO26_GPIO26 1
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_GPIO27_U (REG_IO_MUX_BASE +0x70)
#define FUNC_GPIO27_GPIO27 1
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_GPIO28_U (REG_IO_MUX_BASE +0x74)
#define FUNC_GPIO28_GPIO28 1
#define FUNC_GPIO28_GPIO28_0 0
#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE +0x78)
#define FUNC_GPIO29_GPIO29 1
#define FUNC_GPIO29_GPIO29_0 0
#define PERIPHS_IO_MUX_GPIO30_U (REG_IO_MUX_BASE +0x7c)
#define FUNC_GPIO30_GPIO30 1
#define FUNC_GPIO30_GPIO30_0 0
#define PERIPHS_IO_MUX_GPIO31_U (REG_IO_MUX_BASE +0x80)
#define FUNC_GPIO31_GPIO31 1
#define FUNC_GPIO31_GPIO31_0 0
#define PERIPHS_IO_MUX_GPIO32_U (REG_IO_MUX_BASE +0x84)
#define FUNC_GPIO32_GPIO32 1
#define FUNC_GPIO32_GPIO32_0 0
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_GPIO39_U (REG_IO_MUX_BASE +0xa0)
#define FUNC_GPIO39_GPIO39 1
#define FUNC_GPIO39_GPIO39_0 0
#define PERIPHS_IO_MUX_GPIO40_U (REG_IO_MUX_BASE +0xa4)
#define FUNC_GPIO40_GPIO40 1
#define FUNC_GPIO40_GPIO40_0 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
#define IO_MUX_DATE 0xFFFFFFFF
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x2006050
#define IO_MUX_DATE_VERSION 0x2012310
#endif

7
components/soc/esp32h2/include/soc/periph_defs.h
View File

@@ -112,6 +112,13 @@ typedef enum {
ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE,
ETS_BAK_PMS_VIOLATE_INTR_SOURCE,
ETS_CACHE_CORE0_ACS_INTR_SOURCE,
ETS_TG3_TO_INTR_SOURCE,
ETS_TG3_WDT_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_IEEE802154MAC_INTR_SOURCE,
ETS_IEEE802154BB_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_RTC_BLE_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;

33
components/soc/esp32h2/include/soc/rtc.h
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@@ -69,15 +69,21 @@ extern "C" {
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
#define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18
#define RTC_CNTL_DBIAS_1V05 20
#define RTC_CNTL_DBIAS_1V10 23
#define RTC_CNTL_DBIAS_1V15 25
#define RTC_CNTL_DBIAS_1V20 28
#define RTC_CNTL_DBIAS_1V25 30
#define RTC_CNTL_DBIAS_1V30 31 //voltage is about 1.34v in fact
#define RTC_CNTL_DBIAS_1V00 0
#define RTC_CNTL_DBIAS_1V05 4
#define RTC_CNTL_DBIAS_1V10 5
#define RTC_CNTL_DBIAS_1V15 6
#define RTC_CNTL_DBIAS_1V20 7
/* The value of 1V00 can be adjusted between 0~3*/
#define RTC_CNTL_DIG_DBIAS_0V85 0
#define RTC_CNTL_DIG_DBIAS_0V90 1
#define RTC_CNTL_DIG_DBIAS_0V95 2
#define RTC_CNTL_DIG_DBIAS_1V00 3
#define RTC_CNTL_DIG_DBIAS_1V05 4
#define RTC_CNTL_DIG_DBIAS_1V10 5
#define RTC_CNTL_DIG_DBIAS_1V15 6
#define RTC_CNTL_DIG_DBIAS_1V20 7
#define DELAY_FAST_CLK_SWITCH 3
#define DELAY_SLOW_CLK_SWITCH 300
@@ -122,15 +128,6 @@ set sleep_init default param
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
/*
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
storing in efuse (based on ATE 5k ECO3 chips)
*/
#define K_RTC_MID_MUL10000 215
#define K_DIG_MID_MUL10000 213
#define V_RTC_MID_MUL10000 10800
#define V_DIG_MID_MUL10000 10860
/**
* @brief Possible main XTAL frequency values.
*

22
components/soc/esp32h2/include/soc/rtc_caps.h Normal file
View File

@@ -0,0 +1,22 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
#define RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
#define RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
#define RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (RTC_CNTL_CPU_PD_REG_FILE_NUM * (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))

836
components/soc/esp32h2/include/soc/rtc_cntl_reg.h
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File diff suppressed because it is too large Load Diff

868
components/soc/esp32h2/include/soc/rtc_cntl_struct.h
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File diff suppressed because it is too large Load Diff

21
components/soc/esp32h2/include/soc/rtc_io_caps.h Normal file
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@@ -0,0 +1,21 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
/* No dedicated RTCIO subsystem on ESP32-H2. RTC functions are still supported
* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
#define SOC_RTCIO_PIN_COUNT 0
#define RTCIO_LL_PIN_FUNC 0

750
components/soc/esp32h2/include/soc/sensitive_reg.h
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File diff suppressed because it is too large Load Diff

341
components/soc/esp32h2/include/soc/sensitive_struct.h
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@@ -328,8 +328,77 @@ typedef volatile struct {
} dma_apbperi_adc_dac_pms_constrain_1;
union {
struct {
uint32_t reg_dma_apbperi_pms_monitor_lock: 1; /*dma_apbperi_pms_monitor_lock*/
uint32_t reserved1 : 31;
uint32_t dma_apbperi_ble_sec_pms_constrain_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} dma_apbperi_ble_sec_pms_constrain_0;
union {
struct {
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_0: 2;
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_1: 2;
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_2: 2;
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_3: 2;
uint32_t reserved8: 4;
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_0: 2;
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_1: 2;
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_2: 2;
uint32_t reg_dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_3: 2;
uint32_t reserved20: 4;
uint32_t reserved24: 8;
};
uint32_t val;
} dma_apbperi_ble_sec_pms_constrain_1;
union {
struct {
uint32_t reg_dma_apbperi_white_list_pms_constrain_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} dma_apbperi_white_list_pms_constrain_0;
union {
struct {
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_0: 2;
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_1: 2;
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_2: 2;
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_0_pms_3: 2;
uint32_t reserved8: 4;
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_0: 2;
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_1: 2;
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_2: 2;
uint32_t reg_dma_apbperi_white_list_pms_constrain_sram_world_1_pms_3: 2;
uint32_t reserved20: 4;
uint32_t reserved24: 8;
};
uint32_t val;
} dma_apbperi_white_list_pms_constrain_1;
union {
struct {
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} dma_apbperi_sdio_host_pms_constrain_0;
union {
struct {
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0: 2;
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1: 2;
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2: 2;
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3: 2;
uint32_t reserved8: 4;
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0: 2;
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1: 2;
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2: 2;
uint32_t reg_dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3: 2;
uint32_t reserved20: 4;
uint32_t reserved24: 8;
};
uint32_t val;
} dma_apbperi_sdio_host_pms_constrain_1;
union {
struct {
uint32_t reg_dma_apbperi_pms_monitor_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} dma_apbperi_pms_monitor_0;
@@ -514,7 +583,7 @@ typedef volatile struct {
union {
struct {
uint32_t reg_core_0_dram0_pms_monitor_violate_clr: 1; /*core_0_dram0_pms_monitor_violate_clr*/
uint32_t reg_core_0_dram0_pms_monitor_violate_en: 1; /*core_0_dram0_pms_monitor_violate_en*/
uint32_t reg_core_0_dram0_pms_monitor_violate_en: 1; /*core_0_dram0_pms_monitor_violate_en*/
uint32_t reserved2 : 30;
};
uint32_t val;
@@ -550,9 +619,9 @@ typedef volatile struct {
uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_1: 2; /*core_0_pif_pms_constrain_world_0_g0spi_1*/
uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_0: 2; /*core_0_pif_pms_constrain_world_0_g0spi_0*/
uint32_t reg_core_0_pif_pms_constrain_world_0_gpio: 2; /*core_0_pif_pms_constrain_world_0_gpio*/
uint32_t reg_core_0_pif_pms_constrain_world_0_fe2: 2; /*core_0_pif_pms_constrain_world_0_fe2*/
uint32_t reserved8: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_fe: 2; /*core_0_pif_pms_constrain_world_0_fe*/
uint32_t reg_core_0_pif_pms_constrain_world_0_timer: 2; /*core_0_pif_pms_constrain_world_0_timer*/
uint32_t reserved12: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_rtc: 2; /*core_0_pif_pms_constrain_world_0_rtc*/
uint32_t reg_core_0_pif_pms_constrain_world_0_io_mux: 2; /*core_0_pif_pms_constrain_world_0_io_mux*/
uint32_t reg_core_0_pif_pms_constrain_world_0_wdg: 2; /*core_0_pif_pms_constrain_world_0_wdg*/
@@ -574,12 +643,13 @@ typedef volatile struct {
uint32_t reg_core_0_pif_pms_constrain_world_0_rmt: 2; /*core_0_pif_pms_constrain_world_0_rmt*/
uint32_t reserved12 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_0_ledc: 2; /*core_0_pif_pms_constrain_world_0_ledc*/
uint32_t reserved18 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_0_bb: 2; /*core_0_pif_pms_constrain_world_0_bb*/
uint32_t reserved24 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup: 2; /*core_0_pif_pms_constrain_world_0_timergroup*/
uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1: 2; /*core_0_pif_pms_constrain_world_0_timergroup1*/
uint32_t reg_core_0_pif_pms_constrain_world_0_systimer: 2; /*core_0_pif_pms_constrain_world_0_systimer*/
uint32_t reg_core_0_pif_pms_constrain_world_0_efuse: 2;
uint32_t reserved20: 2;
uint32_t reserved22: 2;
uint32_t reserved24: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_systimer: 2;
};
uint32_t val;
} core_0_pif_pms_constrain_2;
@@ -595,8 +665,8 @@ typedef volatile struct {
uint32_t reserved16 : 6;
uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt: 2; /*core_0_pif_pms_constrain_world_0_rwbt*/
uint32_t reserved24 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_wifimac: 2; /*core_0_pif_pms_constrain_world_0_wifimac*/
uint32_t reg_core_0_pif_pms_constrain_world_0_pwr: 2; /*core_0_pif_pms_constrain_world_0_pwr*/
uint32_t reserved26: 2;
uint32_t reserved28: 2;
uint32_t reserved30 : 2;
};
uint32_t val;
@@ -604,124 +674,155 @@ typedef volatile struct {
union {
struct {
uint32_t reserved0 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_usb_wrap: 2; /*core_0_pif_pms_constrain_world_0_usb_wrap*/
uint32_t reserved2: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_peri: 2; /*core_0_pif_pms_constrain_world_0_crypto_peri*/
uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_dma: 2; /*core_0_pif_pms_constrain_world_0_crypto_dma*/
uint32_t reg_core_0_pif_pms_constrain_world_0_apb_adc: 2; /*core_0_pif_pms_constrain_world_0_apb_adc*/
uint32_t reserved10 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_bt_pwr: 2; /*core_0_pif_pms_constrain_world_0_bt_pwr*/
uint32_t reserved12: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_usb_device: 2; /*core_0_pif_pms_constrain_world_0_usb_device*/
uint32_t reg_core_0_pif_pms_constrain_world_0_system: 2; /*core_0_pif_pms_constrain_world_0_system*/
uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive: 2; /*core_0_pif_pms_constrain_world_0_sensitive*/
uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt: 2; /*core_0_pif_pms_constrain_world_0_interrupt*/
uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy: 2; /*core_0_pif_pms_constrain_world_0_dma_copy*/
uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config: 2; /*core_0_pif_pms_constrain_world_0_cache_config*/
uint32_t reg_core_0_pif_pms_constrain_world_0_ad: 2; /*core_0_pif_pms_constrain_world_0_ad*/
uint32_t reg_core_0_pif_pms_constrain_world_0_dio: 2; /*core_0_pif_pms_constrain_world_0_dio*/
uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller: 2; /*core_0_pif_pms_constrain_world_0_world_controller*/
uint32_t reg_core_0_pif_pms_constrain_world_0_etm: 2; /*core_0_pif_pms_constrain_world_0_system*/
uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup3: 2; /*core_0_pif_pms_constrain_world_0_sensitive*/
uint32_t reg_core_0_pif_pms_constrain_world_0_ble_sec: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_ieee802154mac: 2;
uint32_t reserved24: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_coex: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_rtc_ble_tmr: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_clkrst: 2;
};
uint32_t val;
} core_0_pif_pms_constrain_4;
union {
struct {
uint32_t reg_core_0_pif_pms_constrain_world_1_uart: 2; /*core_0_pif_pms_constrain_world_1_uart*/
uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1: 2; /*core_0_pif_pms_constrain_world_1_g0spi_1*/
uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0: 2; /*core_0_pif_pms_constrain_world_1_g0spi_0*/
uint32_t reg_core_0_pif_pms_constrain_world_1_gpio: 2; /*core_0_pif_pms_constrain_world_1_gpio*/
uint32_t reg_core_0_pif_pms_constrain_world_1_fe2: 2; /*core_0_pif_pms_constrain_world_1_fe2*/
uint32_t reg_core_0_pif_pms_constrain_world_1_fe: 2; /*core_0_pif_pms_constrain_world_1_fe*/
uint32_t reg_core_0_pif_pms_constrain_world_1_timer: 2; /*core_0_pif_pms_constrain_world_1_timer*/
uint32_t reg_core_0_pif_pms_constrain_world_1_rtc: 2; /*core_0_pif_pms_constrain_world_1_rtc*/
uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux: 2; /*core_0_pif_pms_constrain_world_1_io_mux*/
uint32_t reg_core_0_pif_pms_constrain_world_1_wdg: 2; /*core_0_pif_pms_constrain_world_1_wdg*/
uint32_t reserved20 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_misc: 2; /*core_0_pif_pms_constrain_world_1_misc*/
uint32_t reg_core_0_pif_pms_constrain_world_1_i2c: 2; /*core_0_pif_pms_constrain_world_1_i2c*/
uint32_t reserved28 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_uart1: 2; /*core_0_pif_pms_constrain_world_1_uart1*/
uint32_t reg_core_0_pif_pms_constrain_world_0_pvt: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_system: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_ad: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_dio: 2;
uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller: 2;
uint32_t reserved18: 14;
};
uint32_t val;
} core_0_pif_pms_constrain_5;
union {
struct {
uint32_t reg_core_0_pif_pms_constrain_world_1_bt: 2; /*core_0_pif_pms_constrain_world_1_bt*/
uint32_t reserved2 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0: 2; /*core_0_pif_pms_constrain_world_1_i2c_ext0*/
uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0: 2; /*core_0_pif_pms_constrain_world_1_uhci0*/
uint32_t reserved8 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_rmt: 2; /*core_0_pif_pms_constrain_world_1_rmt*/
uint32_t reserved12 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_ledc: 2; /*core_0_pif_pms_constrain_world_1_ledc*/
uint32_t reserved18 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_bb: 2; /*core_0_pif_pms_constrain_world_1_bb*/
uint32_t reserved24 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup: 2; /*core_0_pif_pms_constrain_world_1_timergroup*/
uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1: 2; /*core_0_pif_pms_constrain_world_1_timergroup1*/
uint32_t reg_core_0_pif_pms_constrain_world_1_systimer: 2; /*core_0_pif_pms_constrain_world_1_systimer*/
uint32_t reg_core_0_pif_pms_constrain_world_1_uart: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_gpio: 2;
uint32_t reserved8: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_fe: 2;
uint32_t reserved12: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_rtc: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_wdg: 2;
uint32_t reserved20: 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_misc: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2c: 2;
uint32_t reserved28: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_uart1: 2;
};
uint32_t val;
} core_0_pif_pms_constrain_6;
union {
struct {
uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2: 2; /*core_0_pif_pms_constrain_world_1_spi_2*/
uint32_t reserved2 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2; /*core_0_pif_pms_constrain_world_1_apb_ctrl*/
uint32_t reserved6 : 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2; /*core_0_pif_pms_constrain_world_1_can*/
uint32_t reserved12 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2; /*core_0_pif_pms_constrain_world_1_i2s1*/
uint32_t reserved16 : 6;
uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2; /*core_0_pif_pms_constrain_world_1_rwbt*/
uint32_t reserved24 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_wifimac: 2; /*core_0_pif_pms_constrain_world_1_wifimac*/
uint32_t reg_core_0_pif_pms_constrain_world_1_pwr: 2; /*core_0_pif_pms_constrain_world_1_pwr*/
uint32_t reserved30 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_bt: 2;
uint32_t reserved2: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0: 2;
uint32_t reserved8: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_rmt: 2;
uint32_t reserved12: 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_ledc: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_efuse: 2;
uint32_t reserved20: 2;
uint32_t reserved22: 2;
uint32_t reserved24: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_systimer: 2;
};
uint32_t val;
} core_0_pif_pms_constrain_7;
union {
struct {
uint32_t reserved0 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_usb_wrap: 2; /*core_0_pif_pms_constrain_world_1_usb_wrap*/
uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri: 2; /*core_0_pif_pms_constrain_world_1_crypto_peri*/
uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma: 2; /*core_0_pif_pms_constrain_world_1_crypto_dma*/
uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc: 2; /*core_0_pif_pms_constrain_world_1_apb_adc*/
uint32_t reserved10 : 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_bt_pwr: 2; /*core_0_pif_pms_constrain_world_1_bt_pwr*/
uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device: 2; /*core_0_pif_pms_constrain_world_1_usb_device*/
uint32_t reg_core_0_pif_pms_constrain_world_1_system: 2; /*core_0_pif_pms_constrain_world_1_system*/
uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive: 2; /*core_0_pif_pms_constrain_world_1_sensitive*/
uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt: 2; /*core_0_pif_pms_constrain_world_1_interrupt*/
uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy: 2; /*core_0_pif_pms_constrain_world_1_dma_copy*/
uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config: 2; /*core_0_pif_pms_constrain_world_1_cache_config*/
uint32_t reg_core_0_pif_pms_constrain_world_1_ad: 2; /*core_0_pif_pms_constrain_world_1_ad*/
uint32_t reg_core_0_pif_pms_constrain_world_1_dio: 2; /*core_0_pif_pms_constrain_world_1_dio*/
uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller: 2; /*core_0_pif_pms_constrain_world_1_world_controller*/
uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2: 2;
uint32_t reserved2: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2;
uint32_t reserved6: 4;
uint32_t reg_core_0_pif_pms_constrain_world_1_can: 2;
uint32_t reserved12: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1: 2;
uint32_t reserved16: 6;
uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt: 2;
uint32_t reserved24: 2;
uint32_t reserved26: 2;
uint32_t reserved28: 2;
uint32_t reserved30: 2;
};
uint32_t val;
} core_0_pif_pms_constrain_8;
union {
struct {
uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_0*/
uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_1*/
uint32_t reserved22 : 10;
uint32_t reserved0: 2;
uint32_t reserved2: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc: 2;
uint32_t reserved10: 2;
uint32_t reserved12: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_etm: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup3: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_ble_sec: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_ieee802154mac: 2;
uint32_t reserved24: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_coex: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_rtc_ble_tmr: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_clkrst: 2;
};
uint32_t val;
} core_0_pif_pms_constrain_9;
union {
struct {
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l: 3; /*core_0_pif_pms_constrain_rtcfast_world_0_l*/
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h: 3; /*core_0_pif_pms_constrain_rtcfast_world_0_h*/
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l: 3; /*core_0_pif_pms_constrain_rtcfast_world_1_l*/
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h: 3; /*core_0_pif_pms_constrain_rtcfast_world_1_h*/
uint32_t reserved12 : 20;
uint32_t reg_core_0_pif_pms_constrain_world_1_pvt: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_system: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_ad: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_dio: 2;
uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller: 2;
uint32_t reserved18: 14;
};
uint32_t val;
} core_0_pif_pms_constrain_10;
union {
struct {
uint32_t reg_region_pms_constrain_lock : 1; /*region_pms_constrain_lock*/
uint32_t reserved1 : 31;
uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:11;
uint32_t reg_ore_0_pif_pms_constrain_rtcfast_spltaddr_world_1:11;
uint32_t reserved22: 10;
};
uint32_t val;
} core_0_pif_pms_constrain_11;
union {
struct {
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l: 3;
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h: 3;
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l: 3;
uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h: 3;
uint32_t reserved12: 20;
};
uint32_t val;
} core_0_pif_pms_constrain_12;
union {
struct {
uint32_t region_pms_constrain_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} sensitiveion_pms_constrain_0;
@@ -847,7 +948,7 @@ typedef volatile struct {
uint32_t reg_core_0_pif_pms_monitor_nonword_violate_intr: 1; /*core_0_pif_pms_monitor_nonword_violate_intr*/
uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hsize: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hsize*/
uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hworld: 2; /*core_0_pif_pms_monitor_nonword_violate_status_hworld*/
uint32_t reserved5 : 27;
uint32_t reserved5: 27;
};
uint32_t val;
} core_0_pif_pms_monitor_5;
@@ -865,9 +966,9 @@ typedef volatile struct {
uint32_t reg_backup_bus_pms_constrain_g0spi_1: 2; /*backup_bus_pms_constrain_g0spi_1*/
uint32_t reg_backup_bus_pms_constrain_g0spi_0: 2; /*backup_bus_pms_constrain_g0spi_0*/
uint32_t reg_backup_bus_pms_constrain_gpio: 2; /*backup_bus_pms_constrain_gpio*/
uint32_t reg_backup_bus_pms_constrain_fe2: 2; /*backup_bus_pms_constrain_fe2*/
uint32_t reserved8: 2;
uint32_t reg_backup_bus_pms_constrain_fe: 2; /*backup_bus_pms_constrain_fe*/
uint32_t reg_backup_bus_pms_constrain_timer: 2; /*backup_bus_pms_constrain_timer*/
uint32_t reserved12: 2;
uint32_t reg_backup_bus_pms_constrain_rtc: 2; /*backup_bus_pms_constrain_rtc*/
uint32_t reg_backup_bus_pms_constrain_io_mux: 2; /*backup_bus_pms_constrain_io_mux*/
uint32_t reg_backup_bus_pms_constrain_wdg: 2; /*backup_bus_pms_constrain_wdg*/
@@ -889,8 +990,9 @@ typedef volatile struct {
uint32_t reg_backup_bus_pms_constrain_rmt: 2; /*backup_bus_pms_constrain_rmt*/
uint32_t reserved12 : 4;
uint32_t reg_backup_bus_pms_constrain_ledc: 2; /*backup_bus_pms_constrain_ledc*/
uint32_t reserved18 : 4;
uint32_t reg_backup_bus_pms_constrain_bb: 2; /*backup_bus_pms_constrain_bb*/
uint32_t reg_backup_bus_pms_constrain_efuse: 2;
uint32_t reserved20 : 2;
uint32_t reserved22 : 2;
uint32_t reserved24 : 2;
uint32_t reg_backup_bus_pms_constrain_timergroup: 2; /*backup_bus_pms_constrain_timergroup*/
uint32_t reg_backup_bus_pms_constrain_timergroup1: 2; /*backup_bus_pms_constrain_timergroup1*/
@@ -910,30 +1012,44 @@ typedef volatile struct {
uint32_t reserved16 : 6;
uint32_t reg_backup_bus_pms_constrain_rwbt: 2; /*backup_bus_pms_constrain_rwbt*/
uint32_t reserved24 : 2;
uint32_t reg_backup_bus_pms_constrain_wifimac: 2; /*backup_bus_pms_constrain_wifimac*/
uint32_t reg_backup_bus_pms_constrain_pwr: 2; /*backup_bus_pms_constrain_pwr*/
uint32_t reserved26 : 2;
uint32_t reserved28 : 2;
uint32_t reserved30 : 2;
};
uint32_t val;
} backup_bus_pms_constrain_3;
union {
struct {
uint32_t reserved0 : 2;
uint32_t reg_backup_bus_pms_constrain_usb_wrap: 2; /*backup_bus_pms_constrain_usb_wrap*/
uint32_t reg_backup_bus_pms_constrain_crypto_peri: 2; /*backup_bus_pms_constrain_crypto_peri*/
uint32_t reg_backup_bus_pms_constrain_crypto_dma: 2; /*backup_bus_pms_constrain_crypto_dma*/
uint32_t reg_backup_bus_pms_constrain_apb_adc: 2; /*backup_bus_pms_constrain_apb_adc*/
uint32_t reserved10 : 2;
uint32_t reg_backup_bus_pms_constrain_bt_pwr: 2; /*backup_bus_pms_constrain_bt_pwr*/
uint32_t reg_backup_bus_pms_constrain_usb_device: 2; /*backup_bus_pms_constrain_usb_device*/
uint32_t reserved16 : 16;
uint32_t reserved0: 2;
uint32_t reserved2: 2;
uint32_t reg_backup_bus_pms_constrain_crypto_peri: 2;
uint32_t reg_backup_bus_pms_constrain_crypto_dma: 2;
uint32_t reg_backup_bus_pms_constrain_apb_adc: 2;
uint32_t reserved10: 2;
uint32_t reserved12: 2;
uint32_t reg_backup_bus_pms_constrain_usb_device: 2;
uint32_t reg_backup_bus_pms_constrain_etm: 2;
uint32_t reg_backup_bus_pms_constrain_timergroup3: 2;
uint32_t reg_backup_bus_pms_constrain_ble_sec: 2;
uint32_t backup_bus_pms_constrain_ieee802154mac: 2;
uint32_t reserved24: 2;
uint32_t reg_backup_bus_pms_constrain_coex: 2;
uint32_t reg_backup_bus_pms_constrain_rtc_ble_tmr: 2;
uint32_t reg_backup_bus_pms_constrain_clkrst: 2;
};
uint32_t val;
} backup_bus_pms_constrain_4;
union {
struct {
uint32_t reg_backup_bus_pms_monitor_lock: 1; /*backup_bus_pms_monitor_lock*/
uint32_t reserved1 : 31;
uint32_t backup_bus_pms_constrain_pvt: 2;
uint32_t reserved2: 30;
};
uint32_t val;
} backup_bus_pms_constrain_5;
union {
struct {
uint32_t backup_bus_pms_monitor_lock: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} backup_bus_pms_monitor_0;
@@ -958,9 +1074,8 @@ typedef volatile struct {
uint32_t backup_bus_pms_monitor_3;
union {
struct {
uint32_t reg_clk_en : 1; /*clk_en*/
uint32_t reserved1 : 31;
uint32_t reservedNone : None; /*SENSITIVE_CLOCK_GATE_REG_REG*/
uint32_t reg_clk_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} clock_gate;
@@ -1907,6 +2022,4 @@ extern sensitive_dev_t SENSITIVE;
}
#endif
#endif /*_SOC_SENSITIVE_STRUCT_H_ */

73
components/soc/esp32h2/include/soc/soc.h
View File

@@ -29,52 +29,83 @@
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_EXTMEM_BASE 0x600c4000
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_ITAG_TABLE 0x600c6000
#define DR_REG_DTAG_TABLE 0x600c8000
#define DR_REG_ECC_MULT_BASE 0x60039000
#define DR_REG_AES_BASE 0x6003a000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_RSA_BASE 0x6003c000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_GDMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
// #define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000
#define DR_REG_GPIO_BASE 0x60004000
#define DR_REG_GPIO_SD_BASE 0x60004f00
#define DR_REG_FE2_BASE 0x60005000
#define DR_REG_FE_BASE 0x60006000
#define DR_REG_FRC_TIMER_BASE 0x60007000
#define DR_REG_RTCCNTL_BASE 0x60008000
#define DR_REG_RTCIO_BASE 0x60008400
#define DR_REG_SENS_BASE 0x60008800
#define DR_REG_RTC_I2C_BASE 0x60008C00
#define DR_REG_IO_MUX_BASE 0x60009000
#define DR_REG_RTC_I2C_BASE 0x6000e000
#define DR_REG_HINF_BASE 0x6002B000
#define DR_REG_UHCI1_BASE 0x6000C000
#define DR_REG_I2S_BASE 0x6000F000
#define DR_REG_UART1_BASE 0x60010000
#define DR_REG_BT_BASE 0x60011000
#define DR_REG_I2C_EXT_BASE 0x60013000
#define DR_REG_UHCI0_BASE 0x60014000
#define DR_REG_SLCHOST_BASE 0x60019000
#define DR_REG_RMT_BASE 0x60016000
#define DR_REG_PCNT_BASE 0x60017000
#define DR_REG_SLC_BASE 0x6002D000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_EFUSE_BASE 0x60008800
#define DR_REG_EFUSE_BASE 0x6001A000
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_PWM_BASE 0x6001E000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_RTC_SLOWMEM_BASE 0x60021000
#define DR_REG_SYS_TIMER_BASE 0x60023000
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SPI3_BASE 0x60025000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_I2S0_BASE 0x6002D000
#define DR_REG_I2C1_EXT_BASE 0x60027000
#define DR_REG_SDMMC_BASE 0x60028000
#define DR_REG_CAN_BASE 0x6002B000
#define DR_REG_PWM1_BASE 0x6002C000
#define DR_REG_I2S1_BASE 0x6002D000
#define DR_REG_UART2_BASE 0x6002E000
#define DR_REG_PWM2_BASE 0x6002F000
#define DR_REG_PWM3_BASE 0x60030000
#define DR_REG_SPI4_BASE 0x60037000
#define DR_REG_USB_WRAP_BASE 0x60039000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_LCD_CAM_BASE 0x60041000
#define DR_REG_AES_XTS_BASE 0x600CC000
#define DR_REG_USB_DEVICE_BASE 0x60043000
#define DR_REG_CLKRST_BASE 0x6004B000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000)
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000)
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
@@ -190,19 +221,19 @@
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define APB_CLK_FREQ_ROM ( 32*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM ( 40*1000000)
#define UART_CLK_FREQ_ROM ( 32*1000000)
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ APB_CLK_FREQ
#if CONFIG_IDF_ENV_FPGA
#define APB_CLK_FREQ ( 40*1000000 )
#define APB_CLK_FREQ ( 32*1000000 )
#else
#define APB_CLK_FREQ ( 80*1000000 )
#endif
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define XTAL_CLK_FREQ (40*1000000)
#define XTAL_CLK_FREQ (32*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
@@ -224,7 +255,7 @@
#define SOC_IRAM_HIGH 0x403E0000
#define SOC_DRAM_LOW 0x3FC80000
#define SOC_DRAM_HIGH 0x3FCE0000
#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C3 only has RTC slow memory
#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-H2 only has RTC slow memory
#define SOC_RTC_IRAM_HIGH 0x50002000
#define SOC_RTC_DRAM_LOW 0x50000000
#define SOC_RTC_DRAM_HIGH 0x50002000
@@ -315,7 +346,7 @@
#define ETS_FRC1_INUM 22
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#ifdef CONFIG_IDF_TARGET_ESP32C3
#ifdef CONFIG_IDF_TARGET_ESP32H2
#define ETS_MEMPROT_ERR_INUM 26
#endif
#define ETS_DPORT_INUM 28

38
components/soc/esp32h2/include/soc/spi_caps.h Normal file
View File

@@ -0,0 +1,38 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_DMA_CHAN_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) 3
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72
//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles
#define SOC_SPI_SUPPORT_DDRCLK 1
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2)
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16

371
components/soc/esp32h2/include/soc/spi_reg.h
View File

@@ -51,21 +51,21 @@ clock domain, which is only used in SPI master mode..*/
#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF
#define SPI_USR_ADDR_VALUE_S 0
#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
figured in CONF state..*/
#define SPI_WR_BIT_ORDER (BIT(26))
#define SPI_WR_BIT_ORDER_M (BIT(26))
#define SPI_WR_BIT_ORDER_V 0x1
#define SPI_WR_BIT_ORDER_S 26
/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
tate..*/
#define SPI_RD_BIT_ORDER (BIT(25))
#define SPI_RD_BIT_ORDER_M (BIT(25))
#define SPI_RD_BIT_ORDER_V 0x1
#define SPI_RD_BIT_ORDER_S 25
#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008)
/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB
first. Can be configured in CONF state.*/
#define SPI_WR_BIT_ORDER 0x00000003
#define SPI_WR_BIT_ORDER_M ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
#define SPI_WR_BIT_ORDER_V 0x3
#define SPI_WR_BIT_ORDER_S 25
/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured
in CONF state.*/
#define SPI_RD_BIT_ORDER 0x00000003
#define SPI_RD_BIT_ORDER_M ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
#define SPI_RD_BIT_ORDER_V 0x3
#define SPI_RD_BIT_ORDER_S 23
/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
/*description: Write protect signal output when SPI is idle. 1: output high, 0: output low. C
an be configured in CONF state..*/
@@ -641,6 +641,20 @@ _vld is cleared by spi_trans_done..*/
#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18))
#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1
#define SPI_DMA_SLV_SEG_TRANS_EN_S 18
/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready
for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
#define SPI_DMA_INFIFO_FULL (BIT(1))
#define SPI_DMA_INFIFO_FULL_M (BIT(1))
#define SPI_DMA_INFIFO_FULL_V 0x1
#define SPI_DMA_INFIFO_FULL_S 1
/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready
for sending data. 0: DMA TX FIFO is ready for sending data.*/
#define SPI_DMA_OUTFIFO_EMPTY (BIT(0))
#define SPI_DMA_OUTFIFO_EMPTY_M (BIT(0))
#define SPI_DMA_OUTFIFO_EMPTY_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_S 0
#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
@@ -1178,257 +1192,384 @@ the receive data. 0: Others. .*/
#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0
#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x044)
/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */
/*description: The software set bit for SPI_APP1_INT interrupt.*/
#define SPI_APP1_INT_SET (BIT(20))
#define SPI_APP1_INT_SET_M (BIT(20))
#define SPI_APP1_INT_SET_V 0x1
#define SPI_APP1_INT_SET_S 20
/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
/*description: The software set bit for SPI_APP2_INT interrupt.*/
#define SPI_APP2_INT_SET (BIT(19))
#define SPI_APP2_INT_SET_M (BIT(19))
#define SPI_APP2_INT_SET_V 0x1
#define SPI_APP2_INT_SET_S 19
/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */
/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET (BIT(18))
#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M (BIT(18))
#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V 0x1
#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S 18
/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */
/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M (BIT(17))
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V 0x1
#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S 17
/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
#define SPI_SLV_CMD_ERR_INT_SET (BIT(16))
#define SPI_SLV_CMD_ERR_INT_SET_M (BIT(16))
#define SPI_SLV_CMD_ERR_INT_SET_V 0x1
#define SPI_SLV_CMD_ERR_INT_SET_S 16
/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
#define SPI_SLV_BUF_ADDR_ERR_INT_SET (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M (BIT(15))
#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V 0x1
#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S 15
/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
#define SPI_SEG_MAGIC_ERR_INT_SET (BIT(14))
#define SPI_SEG_MAGIC_ERR_INT_SET_M (BIT(14))
#define SPI_SEG_MAGIC_ERR_INT_SET_V 0x1
#define SPI_SEG_MAGIC_ERR_INT_SET_S 14
/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */
/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
#define SPI_DMA_SEG_TRANS_DONE_INT_SET (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M (BIT(13))
#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V 0x1
#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S 13
/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */
/*description: The software set bit for SPI_TRANS_DONE_INT interrupt.*/
#define SPI_TRANS_DONE_INT_SET (BIT(12))
#define SPI_TRANS_DONE_INT_SET_M (BIT(12))
#define SPI_TRANS_DONE_INT_SET_V 0x1
#define SPI_TRANS_DONE_INT_SET_S 12
/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
#define SPI_SLV_WR_BUF_DONE_INT_SET (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_SET_M (BIT(11))
#define SPI_SLV_WR_BUF_DONE_INT_SET_V 0x1
#define SPI_SLV_WR_BUF_DONE_INT_SET_S 11
/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
#define SPI_SLV_RD_BUF_DONE_INT_SET (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_SET_M (BIT(10))
#define SPI_SLV_RD_BUF_DONE_INT_SET_V 0x1
#define SPI_SLV_RD_BUF_DONE_INT_SET_S 10
/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
#define SPI_SLV_WR_DMA_DONE_INT_SET (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_SET_M (BIT(9))
#define SPI_SLV_WR_DMA_DONE_INT_SET_V 0x1
#define SPI_SLV_WR_DMA_DONE_INT_SET_S 9
/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */
/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
#define SPI_SLV_RD_DMA_DONE_INT_SET (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_SET_M (BIT(8))
#define SPI_SLV_RD_DMA_DONE_INT_SET_V 0x1
#define SPI_SLV_RD_DMA_DONE_INT_SET_S 8
/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave CMDA interrupt.*/
#define SPI_SLV_CMDA_INT_SET (BIT(7))
#define SPI_SLV_CMDA_INT_SET_M (BIT(7))
#define SPI_SLV_CMDA_INT_SET_V 0x1
#define SPI_SLV_CMDA_INT_SET_S 7
/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave CMD9 interrupt.*/
#define SPI_SLV_CMD9_INT_SET (BIT(6))
#define SPI_SLV_CMD9_INT_SET_M (BIT(6))
#define SPI_SLV_CMD9_INT_SET_V 0x1
#define SPI_SLV_CMD9_INT_SET_S 6
/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave CMD8 interrupt.*/
#define SPI_SLV_CMD8_INT_SET (BIT(5))
#define SPI_SLV_CMD8_INT_SET_M (BIT(5))
#define SPI_SLV_CMD8_INT_SET_V 0x1
#define SPI_SLV_CMD8_INT_SET_S 5
/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave CMD7 interrupt.*/
#define SPI_SLV_CMD7_INT_SET (BIT(4))
#define SPI_SLV_CMD7_INT_SET_M (BIT(4))
#define SPI_SLV_CMD7_INT_SET_V 0x1
#define SPI_SLV_CMD7_INT_SET_S 4
/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave En_QPI interrupt.*/
#define SPI_SLV_EN_QPI_INT_SET (BIT(3))
#define SPI_SLV_EN_QPI_INT_SET_M (BIT(3))
#define SPI_SLV_EN_QPI_INT_SET_V 0x1
#define SPI_SLV_EN_QPI_INT_SET_S 3
/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: The software set bit for SPI slave Ex_QPI interrupt.*/
#define SPI_SLV_EX_QPI_INT_SET (BIT(2))
#define SPI_SLV_EX_QPI_INT_SET_M (BIT(2))
#define SPI_SLV_EX_QPI_INT_SET_V 0x1
#define SPI_SLV_EX_QPI_INT_SET_S 2
/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M (BIT(1))
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V 0x1
#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S 1
/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M (BIT(0))
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V 0x1
#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S 0
#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x098)
/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF0 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF0 0xFFFFFFFF
#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S))
#define SPI_BUF0_V 0xFFFFFFFF
#define SPI_BUF0_S 0
#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9C)
#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x09C)
/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF1 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF1 0xFFFFFFFF
#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S))
#define SPI_BUF1_V 0xFFFFFFFF
#define SPI_BUF1_S 0
#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xA0)
#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x0A0)
/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF2 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF2 0xFFFFFFFF
#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S))
#define SPI_BUF2_V 0xFFFFFFFF
#define SPI_BUF2_S 0
#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xA4)
#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x0A4)
/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF3 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF3 0xFFFFFFFF
#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S))
#define SPI_BUF3_V 0xFFFFFFFF
#define SPI_BUF3_S 0
#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xA8)
#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x0A8)
/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF4 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF4 0xFFFFFFFF
#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S))
#define SPI_BUF4_V 0xFFFFFFFF
#define SPI_BUF4_S 0
#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xAC)
#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x0AC)
/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF5 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF5 0xFFFFFFFF
#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S))
#define SPI_BUF5_V 0xFFFFFFFF
#define SPI_BUF5_S 0
#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xB0)
#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x0B0)
/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF6 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF6 0xFFFFFFFF
#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S))
#define SPI_BUF6_V 0xFFFFFFFF
#define SPI_BUF6_S 0
#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xB4)
#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x0B4)
/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF7 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF7 0xFFFFFFFF
#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S))
#define SPI_BUF7_V 0xFFFFFFFF
#define SPI_BUF7_S 0
#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xB8)
#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0x0B8)
/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF8 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF8 0xFFFFFFFF
#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S))
#define SPI_BUF8_V 0xFFFFFFFF
#define SPI_BUF8_S 0
#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xBC)
#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0x0BC)
/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF9 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF9 0xFFFFFFFF
#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S))
#define SPI_BUF9_V 0xFFFFFFFF
#define SPI_BUF9_S 0
#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xC0)
#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0x0C0)
/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF10 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF10 0xFFFFFFFF
#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S))
#define SPI_BUF10_V 0xFFFFFFFF
#define SPI_BUF10_S 0
#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xC4)
#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0x0C4)
/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF11 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF11 0xFFFFFFFF
#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S))
#define SPI_BUF11_V 0xFFFFFFFF
#define SPI_BUF11_S 0
#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xC8)
#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0x0C8)
/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF12 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF12 0xFFFFFFFF
#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S))
#define SPI_BUF12_V 0xFFFFFFFF
#define SPI_BUF12_S 0
#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xCC)
#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0x0CC)
/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF13 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF13 0xFFFFFFFF
#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S))
#define SPI_BUF13_V 0xFFFFFFFF
#define SPI_BUF13_S 0
#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xD0)
#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0x0D0)
/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF14 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF14 0xFFFFFFFF
#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S))
#define SPI_BUF14_V 0xFFFFFFFF
#define SPI_BUF14_S 0
#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xD4)
#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0x0D4)
/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: data buffer.*/
#define SPI_BUF15 0xFFFFFFFF
/*description: data buffer*/
#define SPI_BUF15 0xFFFFFFFF
#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S))
#define SPI_BUF15_V 0xFFFFFFFF
#define SPI_BUF15_S 0
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xE0)
#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x0E0)
/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
ns will start. 0: This is not seg-trans mode..*/
#define SPI_USR_CONF (BIT(28))
/*description: 1: Enable the DMA CONF phase of current seg-trans operation
which means seg-trans will start. 0: This is not seg-trans mode.*/
#define SPI_USR_CONF (BIT(28))
#define SPI_USR_CONF_M (BIT(28))
#define SPI_USR_CONF_V 0x1
#define SPI_USR_CONF_S 28
/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
onfigured in CONF state..*/
#define SPI_SOFT_RESET (BIT(27))
/*description: Software reset enable reset the spi clock line cs line and data
lines. Can be configured in CONF state.*/
#define SPI_SOFT_RESET (BIT(27))
#define SPI_SOFT_RESET_M (BIT(27))
#define SPI_SOFT_RESET_V 0x1
#define SPI_SOFT_RESET_S 27
/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
#define SPI_SLAVE_MODE (BIT(26))
/*description: Set SPI work mode. 1: slave mode 0: master mode.*/
#define SPI_SLAVE_MODE (BIT(26))
#define SPI_SLAVE_MODE_M (BIT(26))
#define SPI_SLAVE_MODE_V 0x1
#define SPI_SLAVE_MODE_S 26
/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
/*description: The magic value of BM table in master DMA seg-trans..*/
#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F
/*description: The magic value of BM table in master DMA seg-trans.*/
#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F
#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF
#define SPI_DMA_SEG_MAGIC_VALUE_S 22
/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
th in CPU controlled mode(Wr_BUF). 0: others.*/
#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11))
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave
data length in CPU controlled mode(Wr_BUF). 0: others*/
#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11))
#define SPI_SLV_WRBUF_BITLEN_EN_M (BIT(11))
#define SPI_SLV_WRBUF_BITLEN_EN_V 0x1
#define SPI_SLV_WRBUF_BITLEN_EN_S 11
/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
n CPU controlled mode(Rd_BUF). 0: others.*/
#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10))
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave
data length in CPU controlled mode(Rd_BUF). 0: others*/
#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10))
#define SPI_SLV_RDBUF_BITLEN_EN_M (BIT(10))
#define SPI_SLV_RDBUF_BITLEN_EN_V 0x1
#define SPI_SLV_RDBUF_BITLEN_EN_S 10
/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
th in DMA controlled mode(Wr_DMA). 0: others.*/
#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9))
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave
data length in DMA controlled mode(Wr_DMA). 0: others*/
#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9))
#define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9))
#define SPI_SLV_WRDMA_BITLEN_EN_V 0x1
#define SPI_SLV_WRDMA_BITLEN_EN_S 9
/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
n DMA controlled mode(Rd_DMA). 0: others.*/
#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8))
/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave
data length in DMA controlled mode(Rd_DMA). 0: others*/
#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8))
#define SPI_SLV_RDDMA_BITLEN_EN_M (BIT(8))
#define SPI_SLV_RDDMA_BITLEN_EN_V 0x1
#define SPI_SLV_RDDMA_BITLEN_EN_S 8
/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
dge 0: output data at tsck posedge .*/
#define SPI_RSCK_DATA_OUT (BIT(3))
/*description: It saves half a cycle when tsck is the same as rsck. 1: output
data at rsck posedge 0: output data at tsck posedge*/
#define SPI_RSCK_DATA_OUT (BIT(3))
#define SPI_RSCK_DATA_OUT_M (BIT(3))
#define SPI_RSCK_DATA_OUT_V 0x1
#define SPI_RSCK_DATA_OUT_S 3
/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
#define SPI_CLK_MODE_13 (BIT(2))
/*description: {CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output
data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/
#define SPI_CLK_MODE_13 (BIT(2))
#define SPI_CLK_MODE_13_M (BIT(2))
#define SPI_CLK_MODE_13_V 0x1
#define SPI_CLK_MODE_13_S 2
/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
#define SPI_CLK_MODE 0x00000003
/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
#define SPI_CLK_MODE 0x00000003
#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
#define SPI_CLK_MODE_V 0x3
#define SPI_CLK_MODE_S 0
#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xE4)
#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x0E4)
/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
/*description: In the slave mode it is the value of address..*/
#define SPI_SLV_LAST_ADDR 0x0000003F
/*description: In the slave mode it is the value of address.*/
#define SPI_SLV_LAST_ADDR 0x0000003F
#define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
#define SPI_SLV_LAST_ADDR_V 0x3F
#define SPI_SLV_LAST_ADDR_S 26
/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
/*description: In the slave mode it is the value of command..*/
#define SPI_SLV_LAST_COMMAND 0x000000FF
/*description: In the slave mode it is the value of command.*/
#define SPI_SLV_LAST_COMMAND 0x000000FF
#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
#define SPI_SLV_LAST_COMMAND_V 0xFF
#define SPI_SLV_LAST_COMMAND_S 18
/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
/*description: The transferred data bit length in SPI slave FD and HD mode. .*/
#define SPI_SLV_DATA_BITLEN 0x0003FFFF
/*description: The transferred data bit length in SPI slave FD and HD mode.*/
#define SPI_SLV_DATA_BITLEN 0x0003FFFF
#define SPI_SLV_DATA_BITLEN_M ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
#define SPI_SLV_DATA_BITLEN_V 0x3FFFF
#define SPI_SLV_DATA_BITLEN_S 0
#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xE8)
#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0x0E8)
/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
M. 0: XTAL CLK..*/
#define SPI_MST_CLK_SEL (BIT(2))
/*description: This bit is used to select SPI module clock source in master
mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
#define SPI_MST_CLK_SEL (BIT(2))
#define SPI_MST_CLK_SEL_M (BIT(2))
#define SPI_MST_CLK_SEL_V 0x1
#define SPI_MST_CLK_SEL_S 2
/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to power on the SPI module clock..*/
#define SPI_MST_CLK_ACTIVE (BIT(1))
/*description: Set this bit to power on the SPI module clock.*/
#define SPI_MST_CLK_ACTIVE (BIT(1))
#define SPI_MST_CLK_ACTIVE_M (BIT(1))
#define SPI_MST_CLK_ACTIVE_V 0x1
#define SPI_MST_CLK_ACTIVE_S 1
/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to enable clk gate.*/
#define SPI_CLK_EN (BIT(0))
/*description: Set this bit to enable clk gate*/
#define SPI_CLK_EN (BIT(0))
#define SPI_CLK_EN_M (BIT(0))
#define SPI_CLK_EN_V 0x1
#define SPI_CLK_EN_S 0
#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xF0)
/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007220 ; */
/*description: SPI register version..*/
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x0F0)
/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101040 ; */
/*description: SPI register version.*/
#define SPI_DATE 0x0FFFFFFF
#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S))
#define SPI_DATE_V 0xFFFFFFF
#define SPI_DATE_S 0

97
components/soc/esp32h2/include/soc/spi_struct.h
View File

@@ -18,6 +18,7 @@
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
typedef volatile struct {
union {
@@ -30,30 +31,30 @@ typedef volatile struct {
};
uint32_t val;
} cmd;
uint32_t addr;
uint32_t addr; /*Address value register*/
union {
struct {
uint32_t reserved0 : 3; /*reserved*/
uint32_t dummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
uint32_t reserved4 : 1; /*reserved*/
uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved7 : 1; /*reserved*/
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved10 : 4; /*reserved*/
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved16 : 1; /*reserved*/
uint32_t reserved17 : 1; /*reserved*/
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
uint32_t reserved22 : 3; /*reserved*/
uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved27 : 5; /*reserved*/
uint32_t reserved0: 3; /*reserved*/
uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
uint32_t reserved4: 1; /*reserved*/
uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved7: 1; /*reserved*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved10: 4; /*reserved*/
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved16: 1; /*reserved*/
uint32_t reserved17: 1; /*reserved*/
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low. Can be configured in CONF state.*/
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/
uint32_t hold_pol: 1; /*SPI_HOLD output value when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/
uint32_t wp_pol: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/
uint32_t reserved22: 1; /*reserved*/
uint32_t rd_bit_order: 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order: 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
uint32_t reserved27: 5; /*reserved*/
};
uint32_t val;
} ctrl;
@@ -178,17 +179,19 @@ typedef volatile struct {
} dout_mode;
union {
struct {
uint32_t reserved0 : 18; /*reserved*/
uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
uint32_t reserved22 : 5; /*reserved*/
uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/
uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/
uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
uint32_t outfifo_empty: 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
uint32_t infifo_full: 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
uint32_t reserved2: 16; /*reserved*/
uint32_t dma_seg_trans_en: 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en: 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
uint32_t tx_seg_trans_clr_en: 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
uint32_t reserved22: 5; /*reserved*/
uint32_t dma_rx_ena: 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/
uint32_t dma_tx_ena: 1; /*Set this bit to enable SPI DMA controlled send data mode.*/
uint32_t rx_afifo_rst: 1; /*Set this bit to reset RX AFIFO which is used to receive data in SPI master and slave mode transfer.*/
uint32_t buf_afifo_rst: 1; /*Set this bit to reset BUF TX AFIFO which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
uint32_t dma_afifo_rst: 1; /*Set this bit to reset DMA TX AFIFO which is used to send data out in SPI slave DMA controlled mode transfer.*/
};
uint32_t val;
} dma_conf;
@@ -300,7 +303,33 @@ typedef volatile struct {
};
uint32_t val;
} dma_int_st;
uint32_t reserved_44;
union {
struct {
uint32_t infifo_full_err_int_set: 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
uint32_t outfifo_empty_err_int_set: 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi_int_set: 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi_int_set: 1; /*The software set bit for SPI slave En_QPI interrupt.*/
uint32_t cmd7_int_set: 1; /*The software set bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8_int_set: 1; /*The software set bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9_int_set: 1; /*The software set bit for SPI slave CMD9 interrupt.*/
uint32_t cmda_int_set: 1; /*The software set bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done_int_set: 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
uint32_t wr_dma_done_int_set: 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
uint32_t rd_buf_done_int_set: 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done_int_set: 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done_int_set: 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
uint32_t dma_seg_trans_done_int_set: 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err_int_set: 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err_int_set: 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err_int_set: 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
uint32_t app2_int_set: 1; /*The software set bit for SPI_APP2_INT interrupt.*/
uint32_t app1_int_set: 1; /*The software set bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21: 11; /*reserved*/
};
uint32_t val;
} dma_int_set;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;

272
components/soc/esp32h2/include/soc/syscon_reg.h
View File

@@ -19,120 +19,6 @@
extern "C" {
#endif
#include "soc.h"
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSCON_RST_TICK_CNT (BIT(12))
#define SYSCON_RST_TICK_CNT_M (BIT(12))
#define SYSCON_RST_TICK_CNT_V 0x1
#define SYSCON_RST_TICK_CNT_S 12
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_EN (BIT(11))
#define SYSCON_CLK_EN_M (BIT(11))
#define SYSCON_CLK_EN_V 0x1
#define SYSCON_CLK_EN_S 11
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_320M_EN (BIT(10))
#define SYSCON_CLK_320M_EN_M (BIT(10))
#define SYSCON_CLK_320M_EN_V 0x1
#define SYSCON_CLK_320M_EN_S 10
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: */
#define SYSCON_PRE_DIV_CNT 0x000003FF
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
#define SYSCON_PRE_DIV_CNT_V 0x3FF
#define SYSCON_PRE_DIV_CNT_S 0
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
/*description: */
#define SYSCON_TICK_ENABLE (BIT(16))
#define SYSCON_TICK_ENABLE_M (BIT(16))
#define SYSCON_TICK_ENABLE_V 0x1
#define SYSCON_TICK_ENABLE_S 16
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
/*description: */
#define SYSCON_CK8M_TICK_NUM 0x000000FF
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
#define SYSCON_CK8M_TICK_NUM_V 0xFF
#define SYSCON_CK8M_TICK_NUM_S 8
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
/*description: */
#define SYSCON_XTAL_TICK_NUM 0x000000FF
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
#define SYSCON_XTAL_TICK_NUM_V 0xFF
#define SYSCON_XTAL_TICK_NUM_S 0
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008)
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_XTAL_OEN (BIT(10))
#define SYSCON_CLK_XTAL_OEN_M (BIT(10))
#define SYSCON_CLK_XTAL_OEN_V 0x1
#define SYSCON_CLK_XTAL_OEN_S 10
/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK40X_BB_OEN (BIT(9))
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
#define SYSCON_CLK40X_BB_OEN_V 0x1
#define SYSCON_CLK40X_BB_OEN_S 9
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8))
#define SYSCON_CLK_DAC_CPU_OEN_V 0x1
#define SYSCON_CLK_DAC_CPU_OEN_S 8
/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7))
#define SYSCON_CLK_ADC_INF_OEN_V 0x1
#define SYSCON_CLK_ADC_INF_OEN_S 7
/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_320M_OEN (BIT(6))
#define SYSCON_CLK_320M_OEN_M (BIT(6))
#define SYSCON_CLK_320M_OEN_V 0x1
#define SYSCON_CLK_320M_OEN_S 6
/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK160_OEN (BIT(5))
#define SYSCON_CLK160_OEN_M (BIT(5))
#define SYSCON_CLK160_OEN_V 0x1
#define SYSCON_CLK160_OEN_S 5
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK80_OEN (BIT(4))
#define SYSCON_CLK80_OEN_M (BIT(4))
#define SYSCON_CLK80_OEN_V 0x1
#define SYSCON_CLK80_OEN_S 4
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK_BB_OEN (BIT(3))
#define SYSCON_CLK_BB_OEN_M (BIT(3))
#define SYSCON_CLK_BB_OEN_V 0x1
#define SYSCON_CLK_BB_OEN_S 3
/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK44_OEN (BIT(2))
#define SYSCON_CLK44_OEN_M (BIT(2))
#define SYSCON_CLK44_OEN_V 0x1
#define SYSCON_CLK44_OEN_S 2
/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK22_OEN (BIT(1))
#define SYSCON_CLK22_OEN_M (BIT(1))
#define SYSCON_CLK22_OEN_V 0x1
#define SYSCON_CLK22_OEN_S 1
/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSCON_CLK20_OEN (BIT(0))
#define SYSCON_CLK20_OEN_M (BIT(0))
#define SYSCON_CLK20_OEN_V 0x1
#define SYSCON_CLK20_OEN_S 0
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C)
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
@@ -149,74 +35,6 @@ extern "C" {
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
#define SYSCON_WIFI_BB_CFG_2_S 0
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014)
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
#define SYSCON_WIFI_CLK_EN_S 0
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018)
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSCON_WIFI_RST 0xFFFFFFFF
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
#define SYSCON_WIFI_RST_S 0
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
/*description: */
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
#define SYSTEM_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits, 6 */
#define SYSTEM_WIFI_CLK_WIFI_EN 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0
#define SYSTEM_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */
#define SYSTEM_WIFI_CLK_BT_EN 0x0
#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
/* Digital team to check */
//bluetooth baseband bit11
#define SYSTEM_BT_BASEBAND_EN BIT(11)
//bluetooth LC bit16 and bit17
#define SYSTEM_BT_LC_EN (BIT(16)|BIT(17))
/* Remaining single bit clock masks */
#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4)
#define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5)
#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12)
#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14)
#define SYSTEM_WIFI_CLK_RNG_EN BIT(15)
#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */
#define SYSTEM_BB_RST BIT(0)
#define SYSTEM_FE_RST BIT(1)
#define SYSTEM_MAC_RST BIT(2)
#define SYSTEM_BT_RST BIT(3)
#define SYSTEM_BTMAC_RST BIT(4)
#define SYSTEM_SDIO_RST BIT(5)
#define SYSTEM_EMAC_RST BIT(7)
#define SYSTEM_MACPWR_RST BIT(8)
#define SYSTEM_RW_BTMAC_RST BIT(9)
#define SYSTEM_RW_BTLP_RST BIT(10)
#define BLE_REG_REST_BIT BIT(11)
#define BLE_PWR_REG_REST_BIT BIT(12)
#define BLE_BB_REG_REST_BIT BIT(13)
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
/*description: */
@@ -438,12 +256,6 @@ extern "C" {
#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27))
#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1
#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27
/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
/*description: */
#define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF
#define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
#define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF
#define SYSCON_RETENTION_LINK_ADDR_S 0
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A4)
/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
@@ -532,30 +344,68 @@ extern "C" {
#define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
#define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F
#define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4
/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
/* SYSCON_PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3))
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V 0x1
#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S 3
/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000007
#define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3
#define SYSCON_PERI_BACKUP_FLOW_ERR_S 1
#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x7
#define SYSCON_PERI_BACKUP_FLOW_ERR_S 0
#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B8)
/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/* SYSCON_PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
#define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define SYSCON_BACKUP_APB_START_ADDR_S 0
#define SYSCON_PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_APB_START_ADDR_M ((SYSCON_PERI_BACKUP_APB_START_ADDR_V)<<(SYSCON_PERI_BACKUP_APB_START_ADDR_S))
#define SYSCON_PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_APB_START_ADDR_S 0
#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC)
/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/* SYSCON_PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
#define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define SYSCON_BACKUP_MEM_START_ADDR_S 0
#define SYSCON_PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MEM_START_ADDR_M ((SYSCON_PERI_BACKUP_MEM_START_ADDR_V)<<(SYSCON_PERI_BACKUP_MEM_START_ADDR_S))
#define SYSCON_PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MEM_START_ADDR_S 0
#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0C0)
#define SYSCON_PERI_BACKUP_MAP0_REG (DR_REG_SYSCON_BASE + 0x0C0)
/* SYSCON_PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_MAP0 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP0_M ((SYSCON_PERI_BACKUP_MAP0_V)<<(SYSCON_PERI_BACKUP_MAP0_S))
#define SYSCON_PERI_BACKUP_MAP0_V 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP0_S 0
#define SYSCON_PERI_BACKUP_MAP1_REG (DR_REG_SYSCON_BASE + 0x0C4)
/* SYSCON_PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_MAP1 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP1_M ((SYSCON_PERI_BACKUP_MAP1_V)<<(SYSCON_PERI_BACKUP_MAP1_S))
#define SYSCON_PERI_BACKUP_MAP1_V 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP1_S 0
#define SYSCON_PERI_BACKUP_MAP2_REG (DR_REG_SYSCON_BASE + 0x0C8)
/* SYSCON_PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_MAP2 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP2_M ((SYSCON_PERI_BACKUP_MAP2_V)<<(SYSCON_PERI_BACKUP_MAP2_S))
#define SYSCON_PERI_BACKUP_MAP2_V 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP2_S 0
#define SYSCON_PERI_BACKUP_MAP3_REG (DR_REG_SYSCON_BASE + 0x0CC)
/* SYSCON_PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_MAP3 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP3_M ((SYSCON_PERI_BACKUP_MAP3_V)<<(SYSCON_PERI_BACKUP_MAP3_S))
#define SYSCON_PERI_BACKUP_MAP3_V 0xFFFFFFFF
#define SYSCON_PERI_BACKUP_MAP3_S 0
#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0D0)
/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1))
@@ -569,7 +419,7 @@ extern "C" {
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0
#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0C4)
#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0D4)
/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1))
@@ -583,7 +433,7 @@ extern "C" {
#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0
#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0C8)
#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0D8)
/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1))
@@ -597,7 +447,7 @@ extern "C" {
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0
#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0D0)
#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0DC)
/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
/*description: */
#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1))
@@ -611,8 +461,16 @@ extern "C" {
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0
#define SYSCON_CLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0E0)
/* SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSCON_CLK_EN (BIT(0))
#define SYSCON_CLK_EN_M (BIT(0))
#define SYSCON_CLK_EN_V 0x1
#define SYSCON_CLK_EN_S 0
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101050 ; */
/*description: Version control*/
#define SYSCON_DATE 0xFFFFFFFF
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))

82
components/soc/esp32h2/include/soc/syscon_struct.h
View File

@@ -18,46 +18,13 @@ extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t apb_ctrl_pre_div_cnt: 10;
uint32_t apb_ctrl_clk_320m_en: 1;
uint32_t clk_en: 1;
uint32_t apb_ctrl_rst_tick_cnt: 1;
uint32_t reserved13: 19;
};
uint32_t val;
} apb_ctrl_sysclk_conf;
union {
struct {
uint32_t apb_ctrl_xtal_tick_num: 8;
uint32_t apb_ctrl_ck8m_tick_num: 8;
uint32_t apb_ctrl_tick_enable: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} apb_ctrl_tick_conf;
union {
struct {
uint32_t clk20_oen: 1;
uint32_t clk22_oen: 1;
uint32_t clk44_oen: 1;
uint32_t clk_bb_oen: 1;
uint32_t clk80_oen: 1;
uint32_t clk160_oen: 1;
uint32_t clk_320m_oen: 1;
uint32_t clk_adc_inf_oen: 1;
uint32_t clk_dac_cpu_oen: 1;
uint32_t clk40x_bb_oen: 1;
uint32_t clk_xtal_oen: 1;
uint32_t reserved11: 21;
};
uint32_t val;
} apb_ctrl_clk_out_en;
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
uint32_t wifi_bb_cfg; /**/
uint32_t wifi_bb_cfg_2; /**/
uint32_t wifi_clk_en; /**/
uint32_t wifi_rst_en; /**/
uint32_t reserved_14;
uint32_t reserved_18;
union {
struct {
uint32_t peri_io_swap: 8;
@@ -223,20 +190,23 @@ typedef volatile struct {
uint32_t rnd_data; /**/
union {
struct {
uint32_t reserved0: 1;
uint32_t peri_backup_flow_err: 2;
uint32_t reserved3: 1;
uint32_t peri_backup_burst_limit: 5;
uint32_t peri_backup_tout_thres: 10;
uint32_t peri_backup_size: 10;
uint32_t peri_backup_start: 1;
uint32_t peri_backup_to_mem: 1;
uint32_t peri_backup_ena: 1;
uint32_t peri_backup_flow_err: 3;
uint32_t peri_backup_addr_map_mode: 1;
uint32_t peri_backup_burst_limit: 5;
uint32_t peri_backup_tout_thres: 10;
uint32_t peri_backup_size: 10;
uint32_t peri_backup_start: 1;
uint32_t peri_backup_to_mem: 1;
uint32_t peri_backup_ena: 1;
};
uint32_t val;
} peri_backup_config;
uint32_t peri_backup_apb_addr; /**/
uint32_t peri_backup_mem_addr; /**/
uint32_t peri_backup_apb_addr; /**/
uint32_t peri_backup_mem_addr; /**/
uint32_t peri_backup_map0; /**/
uint32_t peri_backup_map1; /**/
uint32_t peri_backup_map2; /**/
uint32_t peri_backup_map3; /**/
union {
struct {
uint32_t peri_backup_done: 1;
@@ -261,7 +231,6 @@ typedef volatile struct {
};
uint32_t val;
} peri_backup_int_ena;
uint32_t reserved_cc;
union {
struct {
uint32_t peri_backup_done: 1;
@@ -270,10 +239,13 @@ typedef volatile struct {
};
uint32_t val;
} peri_backup_int_clr;
uint32_t reserved_d4;
uint32_t reserved_d8;
uint32_t reserved_dc;
uint32_t reserved_e0;
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} apb_ctrlclk_conf;
uint32_t reserved_e4;
uint32_t reserved_e8;
uint32_t reserved_ec;
@@ -472,7 +444,7 @@ typedef volatile struct {
uint32_t reserved_3f0;
uint32_t reserved_3f4;
uint32_t reserved_3f8;
uint32_t apb_ctrl_date; /*Version control*/
uint32_t apb_ctrl_date; /*Version control*/
} syscon_dev_t;
extern syscon_dev_t SYSCON;
#ifdef __cplusplus

787
components/soc/esp32h2/include/soc/system_reg.h
View File

@@ -19,6 +19,7 @@
extern "C" {
#endif
#include "soc.h"
#include "clkrst_reg.h"
#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x000)
/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
@@ -60,18 +61,6 @@ extern "C" {
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3))
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1
#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3
/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_PLL_FREQ_SEL (BIT(2))
#define SYSTEM_PLL_FREQ_SEL_M (BIT(2))
#define SYSTEM_PLL_FREQ_SEL_V 0x1
#define SYSTEM_PLL_FREQ_SEL_S 2
/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
/*description: */
#define SYSTEM_CPUPERIOD_SEL 0x00000003
#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
#define SYSTEM_CPUPERIOD_SEL_V 0x3
#define SYSTEM_CPUPERIOD_SEL_S 0
#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x00C)
/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
@@ -81,571 +70,7 @@ extern "C" {
#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1
#define SYSTEM_LSLP_MEM_PD_MASK_S 0
#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x010)
/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
/*description: */
#define SYSTEM_SPI4_CLK_EN (BIT(31))
#define SYSTEM_SPI4_CLK_EN_M (BIT(31))
#define SYSTEM_SPI4_CLK_EN_V 0x1
#define SYSTEM_SPI4_CLK_EN_S 31
/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30))
#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30))
#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1
#define SYSTEM_ADC2_ARB_CLK_EN_S 30
/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_SYSTIMER_CLK_EN (BIT(29))
#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29))
#define SYSTEM_SYSTIMER_CLK_EN_V 0x1
#define SYSTEM_SYSTIMER_CLK_EN_S 29
/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_APB_SARADC_CLK_EN (BIT(28))
#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28))
#define SYSTEM_APB_SARADC_CLK_EN_V 0x1
#define SYSTEM_APB_SARADC_CLK_EN_S 28
/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27))
#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27))
#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1
#define SYSTEM_SPI3_DMA_CLK_EN_S 27
/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM3_CLK_EN (BIT(26))
#define SYSTEM_PWM3_CLK_EN_M (BIT(26))
#define SYSTEM_PWM3_CLK_EN_V 0x1
#define SYSTEM_PWM3_CLK_EN_S 26
/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM2_CLK_EN (BIT(25))
#define SYSTEM_PWM2_CLK_EN_M (BIT(25))
#define SYSTEM_PWM2_CLK_EN_V 0x1
#define SYSTEM_PWM2_CLK_EN_S 25
/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_UART_MEM_CLK_EN (BIT(24))
#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24))
#define SYSTEM_UART_MEM_CLK_EN_V 0x1
#define SYSTEM_UART_MEM_CLK_EN_S 24
/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_USB_DEVICE_CLK_EN (BIT(23))
#define SYSTEM_USB_DEVICE_CLK_EN_M (BIT(23))
#define SYSTEM_USB_DEVICE_CLK_EN_V 0x1
#define SYSTEM_USB_DEVICE_CLK_EN_S 23
/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22))
#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22))
#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1
#define SYSTEM_SPI2_DMA_CLK_EN_S 22
/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S1_CLK_EN (BIT(21))
#define SYSTEM_I2S1_CLK_EN_M (BIT(21))
#define SYSTEM_I2S1_CLK_EN_V 0x1
#define SYSTEM_I2S1_CLK_EN_S 21
/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM1_CLK_EN (BIT(20))
#define SYSTEM_PWM1_CLK_EN_M (BIT(20))
#define SYSTEM_PWM1_CLK_EN_V 0x1
#define SYSTEM_PWM1_CLK_EN_S 20
/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_TWAI_CLK_EN (BIT(19))
#define SYSTEM_TWAI_CLK_EN_M (BIT(19))
#define SYSTEM_TWAI_CLK_EN_V 0x1
#define SYSTEM_TWAI_CLK_EN_S 19
/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18))
#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18))
#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1
#define SYSTEM_I2C_EXT1_CLK_EN_S 18
/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM0_CLK_EN (BIT(17))
#define SYSTEM_PWM0_CLK_EN_M (BIT(17))
#define SYSTEM_PWM0_CLK_EN_V 0x1
#define SYSTEM_PWM0_CLK_EN_S 17
/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_SPI3_CLK_EN (BIT(16))
#define SYSTEM_SPI3_CLK_EN_M (BIT(16))
#define SYSTEM_SPI3_CLK_EN_V 0x1
#define SYSTEM_SPI3_CLK_EN_S 16
/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15))
#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15))
#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1
#define SYSTEM_TIMERGROUP1_CLK_EN_S 15
/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_EFUSE_CLK_EN (BIT(14))
#define SYSTEM_EFUSE_CLK_EN_M (BIT(14))
#define SYSTEM_EFUSE_CLK_EN_V 0x1
#define SYSTEM_EFUSE_CLK_EN_S 14
/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13))
#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13))
#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1
#define SYSTEM_TIMERGROUP_CLK_EN_S 13
/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UHCI1_CLK_EN (BIT(12))
#define SYSTEM_UHCI1_CLK_EN_M (BIT(12))
#define SYSTEM_UHCI1_CLK_EN_V 0x1
#define SYSTEM_UHCI1_CLK_EN_S 12
/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_LEDC_CLK_EN (BIT(11))
#define SYSTEM_LEDC_CLK_EN_M (BIT(11))
#define SYSTEM_LEDC_CLK_EN_V 0x1
#define SYSTEM_LEDC_CLK_EN_S 11
/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PCNT_CLK_EN (BIT(10))
#define SYSTEM_PCNT_CLK_EN_M (BIT(10))
#define SYSTEM_PCNT_CLK_EN_V 0x1
#define SYSTEM_PCNT_CLK_EN_S 10
/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_RMT_CLK_EN (BIT(9))
#define SYSTEM_RMT_CLK_EN_M (BIT(9))
#define SYSTEM_RMT_CLK_EN_V 0x1
#define SYSTEM_RMT_CLK_EN_S 9
/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UHCI0_CLK_EN (BIT(8))
#define SYSTEM_UHCI0_CLK_EN_M (BIT(8))
#define SYSTEM_UHCI0_CLK_EN_V 0x1
#define SYSTEM_UHCI0_CLK_EN_S 8
/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7))
#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7))
#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1
#define SYSTEM_I2C_EXT0_CLK_EN_S 7
/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_SPI2_CLK_EN (BIT(6))
#define SYSTEM_SPI2_CLK_EN_M (BIT(6))
#define SYSTEM_SPI2_CLK_EN_V 0x1
#define SYSTEM_SPI2_CLK_EN_S 6
/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_UART1_CLK_EN (BIT(5))
#define SYSTEM_UART1_CLK_EN_M (BIT(5))
#define SYSTEM_UART1_CLK_EN_V 0x1
#define SYSTEM_UART1_CLK_EN_S 5
/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S0_CLK_EN (BIT(4))
#define SYSTEM_I2S0_CLK_EN_M (BIT(4))
#define SYSTEM_I2S0_CLK_EN_V 0x1
#define SYSTEM_I2S0_CLK_EN_S 4
/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_WDG_CLK_EN (BIT(3))
#define SYSTEM_WDG_CLK_EN_M (BIT(3))
#define SYSTEM_WDG_CLK_EN_V 0x1
#define SYSTEM_WDG_CLK_EN_S 3
/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_UART_CLK_EN (BIT(2))
#define SYSTEM_UART_CLK_EN_M (BIT(2))
#define SYSTEM_UART_CLK_EN_V 0x1
#define SYSTEM_UART_CLK_EN_S 2
/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_SPI01_CLK_EN (BIT(1))
#define SYSTEM_SPI01_CLK_EN_M (BIT(1))
#define SYSTEM_SPI01_CLK_EN_V 0x1
#define SYSTEM_SPI01_CLK_EN_S 1
/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_TIMERS_CLK_EN (BIT(0))
#define SYSTEM_TIMERS_CLK_EN_M (BIT(0))
#define SYSTEM_TIMERS_CLK_EN_V 0x1
#define SYSTEM_TIMERS_CLK_EN_S 0
#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x014)
/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_TSENS_CLK_EN (BIT(10))
#define SYSTEM_TSENS_CLK_EN_M (BIT(10))
#define SYSTEM_TSENS_CLK_EN_V 0x1
#define SYSTEM_TSENS_CLK_EN_S 10
/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_UART2_CLK_EN (BIT(9))
#define SYSTEM_UART2_CLK_EN_M (BIT(9))
#define SYSTEM_UART2_CLK_EN_V 0x1
#define SYSTEM_UART2_CLK_EN_S 9
/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_LCD_CAM_CLK_EN (BIT(8))
#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8))
#define SYSTEM_LCD_CAM_CLK_EN_V 0x1
#define SYSTEM_LCD_CAM_CLK_EN_S 8
/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7))
#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7))
#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1
#define SYSTEM_SDIO_HOST_CLK_EN_S 7
/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_DMA_CLK_EN (BIT(6))
#define SYSTEM_DMA_CLK_EN_M (BIT(6))
#define SYSTEM_DMA_CLK_EN_V 0x1
#define SYSTEM_DMA_CLK_EN_S 6
/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5))
#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5))
#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5
/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4))
#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4))
#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_DS_CLK_EN_S 4
/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3))
#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3))
#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3
/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2))
#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2))
#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2
/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1))
#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1))
#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1
#define SYSTEM_CRYPTO_AES_CLK_EN_S 1
#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x018)
/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
/*description: */
#define SYSTEM_SPI4_RST (BIT(31))
#define SYSTEM_SPI4_RST_M (BIT(31))
#define SYSTEM_SPI4_RST_V 0x1
#define SYSTEM_SPI4_RST_S 31
/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_ADC2_ARB_RST (BIT(30))
#define SYSTEM_ADC2_ARB_RST_M (BIT(30))
#define SYSTEM_ADC2_ARB_RST_V 0x1
#define SYSTEM_ADC2_ARB_RST_S 30
/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_SYSTIMER_RST (BIT(29))
#define SYSTEM_SYSTIMER_RST_M (BIT(29))
#define SYSTEM_SYSTIMER_RST_V 0x1
#define SYSTEM_SYSTIMER_RST_S 29
/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_APB_SARADC_RST (BIT(28))
#define SYSTEM_APB_SARADC_RST_M (BIT(28))
#define SYSTEM_APB_SARADC_RST_V 0x1
#define SYSTEM_APB_SARADC_RST_S 28
/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_SPI3_DMA_RST (BIT(27))
#define SYSTEM_SPI3_DMA_RST_M (BIT(27))
#define SYSTEM_SPI3_DMA_RST_V 0x1
#define SYSTEM_SPI3_DMA_RST_S 27
/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM3_RST (BIT(26))
#define SYSTEM_PWM3_RST_M (BIT(26))
#define SYSTEM_PWM3_RST_V 0x1
#define SYSTEM_PWM3_RST_S 26
/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM2_RST (BIT(25))
#define SYSTEM_PWM2_RST_M (BIT(25))
#define SYSTEM_PWM2_RST_V 0x1
#define SYSTEM_PWM2_RST_S 25
/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UART_MEM_RST (BIT(24))
#define SYSTEM_UART_MEM_RST_M (BIT(24))
#define SYSTEM_UART_MEM_RST_V 0x1
#define SYSTEM_UART_MEM_RST_S 24
/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_USB_DEVICE_RST (BIT(23))
#define SYSTEM_USB_DEVICE_RST_M (BIT(23))
#define SYSTEM_USB_DEVICE_RST_V 0x1
#define SYSTEM_USB_DEVICE_RST_S 23
/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_SPI2_DMA_RST (BIT(22))
#define SYSTEM_SPI2_DMA_RST_M (BIT(22))
#define SYSTEM_SPI2_DMA_RST_V 0x1
#define SYSTEM_SPI2_DMA_RST_S 22
/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S1_RST (BIT(21))
#define SYSTEM_I2S1_RST_M (BIT(21))
#define SYSTEM_I2S1_RST_V 0x1
#define SYSTEM_I2S1_RST_S 21
/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM1_RST (BIT(20))
#define SYSTEM_PWM1_RST_M (BIT(20))
#define SYSTEM_PWM1_RST_V 0x1
#define SYSTEM_PWM1_RST_S 20
/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_TWAI_RST (BIT(19))
#define SYSTEM_TWAI_RST_M (BIT(19))
#define SYSTEM_TWAI_RST_V 0x1
#define SYSTEM_TWAI_RST_S 19
/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2C_EXT1_RST (BIT(18))
#define SYSTEM_I2C_EXT1_RST_M (BIT(18))
#define SYSTEM_I2C_EXT1_RST_V 0x1
#define SYSTEM_I2C_EXT1_RST_S 18
/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PWM0_RST (BIT(17))
#define SYSTEM_PWM0_RST_M (BIT(17))
#define SYSTEM_PWM0_RST_V 0x1
#define SYSTEM_PWM0_RST_S 17
/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_SPI3_RST (BIT(16))
#define SYSTEM_SPI3_RST_M (BIT(16))
#define SYSTEM_SPI3_RST_V 0x1
#define SYSTEM_SPI3_RST_S 16
/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_TIMERGROUP1_RST (BIT(15))
#define SYSTEM_TIMERGROUP1_RST_M (BIT(15))
#define SYSTEM_TIMERGROUP1_RST_V 0x1
#define SYSTEM_TIMERGROUP1_RST_S 15
/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_EFUSE_RST (BIT(14))
#define SYSTEM_EFUSE_RST_M (BIT(14))
#define SYSTEM_EFUSE_RST_V 0x1
#define SYSTEM_EFUSE_RST_S 14
/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_TIMERGROUP_RST (BIT(13))
#define SYSTEM_TIMERGROUP_RST_M (BIT(13))
#define SYSTEM_TIMERGROUP_RST_V 0x1
#define SYSTEM_TIMERGROUP_RST_S 13
/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UHCI1_RST (BIT(12))
#define SYSTEM_UHCI1_RST_M (BIT(12))
#define SYSTEM_UHCI1_RST_V 0x1
#define SYSTEM_UHCI1_RST_S 12
/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_LEDC_RST (BIT(11))
#define SYSTEM_LEDC_RST_M (BIT(11))
#define SYSTEM_LEDC_RST_V 0x1
#define SYSTEM_LEDC_RST_S 11
/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_PCNT_RST (BIT(10))
#define SYSTEM_PCNT_RST_M (BIT(10))
#define SYSTEM_PCNT_RST_V 0x1
#define SYSTEM_PCNT_RST_S 10
/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_RMT_RST (BIT(9))
#define SYSTEM_RMT_RST_M (BIT(9))
#define SYSTEM_RMT_RST_V 0x1
#define SYSTEM_RMT_RST_S 9
/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UHCI0_RST (BIT(8))
#define SYSTEM_UHCI0_RST_M (BIT(8))
#define SYSTEM_UHCI0_RST_V 0x1
#define SYSTEM_UHCI0_RST_S 8
/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2C_EXT0_RST (BIT(7))
#define SYSTEM_I2C_EXT0_RST_M (BIT(7))
#define SYSTEM_I2C_EXT0_RST_V 0x1
#define SYSTEM_I2C_EXT0_RST_S 7
/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_SPI2_RST (BIT(6))
#define SYSTEM_SPI2_RST_M (BIT(6))
#define SYSTEM_SPI2_RST_V 0x1
#define SYSTEM_SPI2_RST_S 6
/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UART1_RST (BIT(5))
#define SYSTEM_UART1_RST_M (BIT(5))
#define SYSTEM_UART1_RST_V 0x1
#define SYSTEM_UART1_RST_S 5
/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_I2S0_RST (BIT(4))
#define SYSTEM_I2S0_RST_M (BIT(4))
#define SYSTEM_I2S0_RST_V 0x1
#define SYSTEM_I2S0_RST_S 4
/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_WDG_RST (BIT(3))
#define SYSTEM_WDG_RST_M (BIT(3))
#define SYSTEM_WDG_RST_V 0x1
#define SYSTEM_WDG_RST_S 3
/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UART_RST (BIT(2))
#define SYSTEM_UART_RST_M (BIT(2))
#define SYSTEM_UART_RST_V 0x1
#define SYSTEM_UART_RST_S 2
/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_SPI01_RST (BIT(1))
#define SYSTEM_SPI01_RST_M (BIT(1))
#define SYSTEM_SPI01_RST_V 0x1
#define SYSTEM_SPI01_RST_S 1
/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_TIMERS_RST (BIT(0))
#define SYSTEM_TIMERS_RST_M (BIT(0))
#define SYSTEM_TIMERS_RST_V 0x1
#define SYSTEM_TIMERS_RST_S 0
#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x01C)
/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_TSENS_RST (BIT(10))
#define SYSTEM_TSENS_RST_M (BIT(10))
#define SYSTEM_TSENS_RST_V 0x1
#define SYSTEM_TSENS_RST_S 10
/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_UART2_RST (BIT(9))
#define SYSTEM_UART2_RST_M (BIT(9))
#define SYSTEM_UART2_RST_V 0x1
#define SYSTEM_UART2_RST_S 9
/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_LCD_CAM_RST (BIT(8))
#define SYSTEM_LCD_CAM_RST_M (BIT(8))
#define SYSTEM_LCD_CAM_RST_V 0x1
#define SYSTEM_LCD_CAM_RST_S 8
/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_SDIO_HOST_RST (BIT(7))
#define SYSTEM_SDIO_HOST_RST_M (BIT(7))
#define SYSTEM_SDIO_HOST_RST_V 0x1
#define SYSTEM_SDIO_HOST_RST_S 7
/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_DMA_RST (BIT(6))
#define SYSTEM_DMA_RST_M (BIT(6))
#define SYSTEM_DMA_RST_V 0x1
#define SYSTEM_DMA_RST_S 6
/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_CRYPTO_HMAC_RST (BIT(5))
#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5))
#define SYSTEM_CRYPTO_HMAC_RST_V 0x1
#define SYSTEM_CRYPTO_HMAC_RST_S 5
/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_CRYPTO_DS_RST (BIT(4))
#define SYSTEM_CRYPTO_DS_RST_M (BIT(4))
#define SYSTEM_CRYPTO_DS_RST_V 0x1
#define SYSTEM_CRYPTO_DS_RST_S 4
/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_CRYPTO_RSA_RST (BIT(3))
#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3))
#define SYSTEM_CRYPTO_RSA_RST_V 0x1
#define SYSTEM_CRYPTO_RSA_RST_S 3
/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_CRYPTO_SHA_RST (BIT(2))
#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2))
#define SYSTEM_CRYPTO_SHA_RST_V 0x1
#define SYSTEM_CRYPTO_SHA_RST_S 2
/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_CRYPTO_AES_RST (BIT(1))
#define SYSTEM_CRYPTO_AES_RST_M (BIT(1))
#define SYSTEM_CRYPTO_AES_RST_V 0x1
#define SYSTEM_CRYPTO_AES_RST_S 1
#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x020)
/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
/*description: */
#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF
#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_NUM_S 0
#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x024)
/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_LPCLK_RTC_EN (BIT(28))
#define SYSTEM_LPCLK_RTC_EN_M (BIT(28))
#define SYSTEM_LPCLK_RTC_EN_V 0x1
#define SYSTEM_LPCLK_RTC_EN_S 28
/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27))
#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27))
#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1
#define SYSTEM_LPCLK_SEL_XTAL32K_S 27
/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_LPCLK_SEL_XTAL (BIT(26))
#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26))
#define SYSTEM_LPCLK_SEL_XTAL_V 0x1
#define SYSTEM_LPCLK_SEL_XTAL_S 26
/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_LPCLK_SEL_8M (BIT(25))
#define SYSTEM_LPCLK_SEL_8M_M (BIT(25))
#define SYSTEM_LPCLK_SEL_8M_V 0x1
#define SYSTEM_LPCLK_SEL_8M_S 25
/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24))
#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24))
#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1
#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24
/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
/*description: */
#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF
#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_A_S 12
/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
/*description: */
#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF
#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF
#define SYSTEM_BT_LPCK_DIV_B_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x028)
#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x010)
/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0))
@@ -653,7 +78,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x02C)
#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x014)
/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0))
@@ -661,7 +86,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x030)
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x018)
/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0))
@@ -669,7 +94,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x034)
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x01C)
/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0))
@@ -677,7 +102,7 @@ extern "C" {
#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1
#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0
#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038)
#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x020)
/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2))
@@ -697,7 +122,7 @@ extern "C" {
#define SYSTEM_RSA_MEM_PD_V 0x1
#define SYSTEM_RSA_MEM_PD_S 0
#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x03C)
#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x024)
/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_EDMA_RESET (BIT(1))
@@ -711,7 +136,7 @@ extern "C" {
#define SYSTEM_EDMA_CLK_ON_V 0x1
#define SYSTEM_EDMA_CLK_ON_S 0
#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x040)
#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x028)
/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_DCACHE_RESET (BIT(3))
@@ -737,7 +162,7 @@ extern "C" {
#define SYSTEM_ICACHE_CLK_ON_V 0x1
#define SYSTEM_ICACHE_CLK_ON_S 0
#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x044)
#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x02C)
/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
@@ -763,7 +188,7 @@ extern "C" {
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1
#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x048)
#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x030)
/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31))
@@ -789,7 +214,7 @@ extern "C" {
#define SYSTEM_RTC_MEM_CRC_START_V 0x1
#define SYSTEM_RTC_MEM_CRC_START_S 8
#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x04C)
#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x034)
/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
/*description: */
#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF
@@ -797,7 +222,7 @@ extern "C" {
#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF
#define SYSTEM_RTC_MEM_CRC_RES_S 0
#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x050)
#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x038)
/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1))
@@ -811,7 +236,7 @@ extern "C" {
#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1
#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0
#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x054)
#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x03C)
/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
/*description: */
#define SYSTEM_CLK_EN (BIT(0))
@@ -819,33 +244,7 @@ extern "C" {
#define SYSTEM_CLK_EN_V 0x1
#define SYSTEM_CLK_EN_S 0
#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x058)
/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
/*description: */
#define SYSTEM_CLK_DIV_EN (BIT(19))
#define SYSTEM_CLK_DIV_EN_M (BIT(19))
#define SYSTEM_CLK_DIV_EN_V 0x1
#define SYSTEM_CLK_DIV_EN_S 19
/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
/*description: */
#define SYSTEM_CLK_XTAL_FREQ 0x0000007F
#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
#define SYSTEM_CLK_XTAL_FREQ_V 0x7F
#define SYSTEM_CLK_XTAL_FREQ_S 12
/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
/*description: */
#define SYSTEM_SOC_CLK_SEL 0x00000003
#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
#define SYSTEM_SOC_CLK_SEL_V 0x3
#define SYSTEM_SOC_CLK_SEL_S 10
/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
/*description: */
#define SYSTEM_PRE_DIV_CNT 0x000003FF
#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
#define SYSTEM_PRE_DIV_CNT_V 0x3FF
#define SYSTEM_PRE_DIV_CNT_S 0
#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x05C)
#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x040)
/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
/*description: */
#define SYSTEM_MEM_VT_SEL 0x00000003
@@ -877,164 +276,8 @@ extern "C" {
#define SYSTEM_MEM_PATH_LEN_V 0xF
#define SYSTEM_MEM_PATH_LEN_S 0
#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x060)
/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x1
#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6
/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5))
#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (BIT(5))
#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x1
#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5
/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
/*description: */
#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001F
#define SYSTEM_COMB_PATH_LEN_LVT_M ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
#define SYSTEM_COMB_PATH_LEN_LVT_V 0x1F
#define SYSTEM_COMB_PATH_LEN_LVT_S 0
#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x064)
/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x1
#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6
/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5))
#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (BIT(5))
#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x1
#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5
/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
/*description: */
#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001F
#define SYSTEM_COMB_PATH_LEN_NVT_M ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
#define SYSTEM_COMB_PATH_LEN_NVT_V 0x1F
#define SYSTEM_COMB_PATH_LEN_NVT_S 0
#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x068)
/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (BIT(6))
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x1
#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6
/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */
/*description: */
#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5))
#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (BIT(5))
#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x1
#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5
/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
/*description: */
#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001F
#define SYSTEM_COMB_PATH_LEN_HVT_M ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
#define SYSTEM_COMB_PATH_LEN_HVT_V 0x1F
#define SYSTEM_COMB_PATH_LEN_HVT_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x06C)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x070)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x074)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x078)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x07C)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x080)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x084)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x088)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x08C)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0
#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x090)
/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0
#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x094)
/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0
#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x098)
/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
/*description: */
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000FFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0xFFFF
#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0
#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC)
/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007150 ; */
/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2103240 ; */
/*description: */
#define SYSTEM_DATE 0x0FFFFFFF
#define SYSTEM_DATE_M ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))

274
components/soc/esp32h2/include/soc/system_struct.h
View File

@@ -56,134 +56,6 @@ typedef volatile struct {
};
uint32_t val;
} mem_pd_mask;
union {
struct {
uint32_t reg_timers_clk_en : 1; /*reg_timers_clk_en*/
uint32_t reg_spi01_clk_en : 1; /*reg_spi01_clk_en*/
uint32_t reg_uart_clk_en : 1; /*reg_uart_clk_en*/
uint32_t reg_wdg_clk_en : 1; /*reg_wdg_clk_en*/
uint32_t reg_i2s0_clk_en : 1; /*reg_i2s0_clk_en*/
uint32_t reg_uart1_clk_en : 1; /*reg_uart1_clk_en*/
uint32_t reg_spi2_clk_en : 1; /*reg_spi2_clk_en*/
uint32_t reg_i2c_ext0_clk_en : 1; /*reg_i2c_ext0_clk_en*/
uint32_t reg_uhci0_clk_en : 1; /*reg_uhci0_clk_en*/
uint32_t reg_rmt_clk_en : 1; /*reg_rmt_clk_en*/
uint32_t reg_pcnt_clk_en : 1; /*reg_pcnt_clk_en*/
uint32_t reg_ledc_clk_en : 1; /*reg_ledc_clk_en*/
uint32_t reg_uhci1_clk_en : 1; /*reg_uhci1_clk_en*/
uint32_t reg_timergroup_clk_en : 1; /*reg_timergroup_clk_en*/
uint32_t reg_efuse_clk_en : 1; /*reg_efuse_clk_en*/
uint32_t reg_timergroup1_clk_en : 1; /*reg_timergroup1_clk_en*/
uint32_t reg_spi3_clk_en : 1; /*reg_spi3_clk_en*/
uint32_t reg_pwm0_clk_en : 1; /*reg_pwm0_clk_en*/
uint32_t reg_i2c_ext1_clk_en : 1; /*reg_i2c_ext1_clk_en*/
uint32_t reg_can_clk_en : 1; /*reg_can_clk_en*/
uint32_t reg_pwm1_clk_en : 1; /*reg_pwm1_clk_en*/
uint32_t reg_i2s1_clk_en : 1; /*reg_i2s1_clk_en*/
uint32_t reg_spi2_dma_clk_en : 1; /*reg_spi2_dma_clk_en*/
uint32_t reg_usb_device_clk_en : 1; /*reg_usb_device_clk_en*/
uint32_t reg_uart_mem_clk_en : 1; /*reg_uart_mem_clk_en*/
uint32_t reg_pwm2_clk_en : 1; /*reg_pwm2_clk_en*/
uint32_t reg_pwm3_clk_en : 1; /*reg_pwm3_clk_en*/
uint32_t reg_spi3_dma_clk_en : 1; /*reg_spi3_dma_clk_en*/
uint32_t reg_apb_saradc_clk_en : 1; /*reg_apb_saradc_clk_en*/
uint32_t reg_systimer_clk_en : 1; /*reg_systimer_clk_en*/
uint32_t reg_adc2_arb_clk_en : 1; /*reg_adc2_arb_clk_en*/
uint32_t reg_spi4_clk_en : 1; /*reg_spi4_clk_en*/
};
uint32_t val;
} perip_clk_en0;
union {
struct {
uint32_t reserved0 : 1; /*peripheral reset register*/
uint32_t reg_crypto_aes_clk_en : 1; /*reg_crypto_aes_clk_en*/
uint32_t reg_crypto_sha_clk_en : 1; /*reg_crypto_sha_clk_en*/
uint32_t reg_crypto_rsa_clk_en : 1; /*reg_crypto_rsa_clk_en*/
uint32_t reg_crypto_ds_clk_en : 1; /*reg_crypto_ds_clk_en*/
uint32_t reg_crypto_hmac_clk_en : 1; /*reg_crypto_hmac_clk_en*/
uint32_t reg_dma_clk_en : 1; /*reg_dma_clk_en*/
uint32_t reg_sdio_host_clk_en : 1; /*reg_sdio_host_clk_en*/
uint32_t reg_lcd_cam_clk_en : 1; /*reg_lcd_cam_clk_en*/
uint32_t reg_uart2_clk_en : 1; /*reg_uart2_clk_en*/
uint32_t reg_tsens_clk_en : 1; /*reg_tsens_clk_en*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} perip_clk_en1;
union {
struct {
uint32_t reg_timers_rst : 1; /*reg_timers_rst*/
uint32_t reg_spi01_rst : 1; /*reg_spi01_rst*/
uint32_t reg_uart_rst : 1; /*reg_uart_rst*/
uint32_t reg_wdg_rst : 1; /*reg_wdg_rst*/
uint32_t reg_i2s0_rst : 1; /*reg_i2s0_rst*/
uint32_t reg_uart1_rst : 1; /*reg_uart1_rst*/
uint32_t reg_spi2_rst : 1; /*reg_spi2_rst*/
uint32_t reg_i2c_ext0_rst : 1; /*reg_i2c_ext0_rst*/
uint32_t reg_uhci0_rst : 1; /*reg_uhci0_rst*/
uint32_t reg_rmt_rst : 1; /*reg_rmt_rst*/
uint32_t reg_pcnt_rst : 1; /*reg_pcnt_rst*/
uint32_t reg_ledc_rst : 1; /*reg_ledc_rst*/
uint32_t reg_uhci1_rst : 1; /*reg_uhci1_rst*/
uint32_t reg_timergroup_rst : 1; /*reg_timergroup_rst*/
uint32_t reg_efuse_rst : 1; /*reg_efuse_rst*/
uint32_t reg_timergroup1_rst : 1; /*reg_timergroup1_rst*/
uint32_t reg_spi3_rst : 1; /*reg_spi3_rst*/
uint32_t reg_pwm0_rst : 1; /*reg_pwm0_rst*/
uint32_t reg_i2c_ext1_rst : 1; /*reg_i2c_ext1_rst*/
uint32_t reg_can_rst : 1; /*reg_can_rst*/
uint32_t reg_pwm1_rst : 1; /*reg_pwm1_rst*/
uint32_t reg_i2s1_rst : 1; /*reg_i2s1_rst*/
uint32_t reg_spi2_dma_rst : 1; /*reg_spi2_dma_rst*/
uint32_t reg_usb_device_rst : 1; /*reg_usb_device_rst*/
uint32_t reg_uart_mem_rst : 1; /*reg_uart_mem_rst*/
uint32_t reg_pwm2_rst : 1; /*reg_pwm2_rst*/
uint32_t reg_pwm3_rst : 1; /*reg_pwm3_rst*/
uint32_t reg_spi3_dma_rst : 1; /*reg_spi3_dma_rst*/
uint32_t reg_apb_saradc_rst : 1; /*reg_apb_saradc_rst*/
uint32_t reg_systimer_rst : 1; /*reg_systimer_rst*/
uint32_t reg_adc2_arb_rst : 1; /*reg_adc2_arb_rst*/
uint32_t reg_spi4_rst : 1; /*reg_spi4_rst*/
};
uint32_t val;
} perip_rst_en0;
union {
struct {
uint32_t reserved0 : 1; /*reserved*/
uint32_t reg_crypto_aes_rst : 1; /*reg_crypto_aes_rst*/
uint32_t reg_crypto_sha_rst : 1; /*reg_crypto_sha_rst*/
uint32_t reg_crypto_rsa_rst : 1; /*reg_crypto_rsa_rst*/
uint32_t reg_crypto_ds_rst : 1; /*reg_crypto_ds_rst*/
uint32_t reg_crypto_hmac_rst : 1; /*reg_crypto_hmac_rst*/
uint32_t reg_dma_rst : 1; /*reg_dma_rst*/
uint32_t reg_sdio_host_rst : 1; /*reg_sdio_host_rst*/
uint32_t reg_lcd_cam_rst : 1; /*reg_lcd_cam_rst*/
uint32_t reg_uart2_rst : 1; /*reg_uart2_rst*/
uint32_t reg_tsens_rst : 1; /*reg_tsens_rst*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} perip_rst_en1;
union {
struct {
uint32_t reg_bt_lpck_div_num : 12; /*reg_bt_lpck_div_num*/
uint32_t reserved12 : 20; /*reserved*/
};
uint32_t val;
} bt_lpck_div_int;
union {
struct {
uint32_t reg_bt_lpck_div_b : 12; /*reg_bt_lpck_div_b*/
uint32_t reg_bt_lpck_div_a : 12; /*reg_bt_lpck_div_a*/
uint32_t reg_lpclk_sel_rtc_slow : 1; /*reg_lpclk_sel_rtc_slow*/
uint32_t reg_lpclk_sel_8m : 1; /*reg_lpclk_sel_8m*/
uint32_t reg_lpclk_sel_xtal : 1; /*reg_lpclk_sel_xtal*/
uint32_t reg_lpclk_sel_xtal32k : 1; /*reg_lpclk_sel_xtal32k*/
uint32_t reg_lpclk_rtc_en : 1; /*reg_lpclk_rtc_en*/
uint32_t reserved29 : 3; /*reserved*/
};
uint32_t val;
} bt_lpck_div_frac;
union {
struct {
uint32_t reg_cpu_intr_from_cpu_0 : 1; /*reg_cpu_intr_from_cpu_0*/
@@ -275,16 +147,6 @@ typedef volatile struct {
};
uint32_t val;
} clock_gate;
union {
struct {
uint32_t reg_pre_div_cnt : 10; /*reg_pre_div_cnt*/
uint32_t reg_soc_clk_sel : 2; /*reg_soc_clk_sel*/
uint32_t reg_clk_xtal_freq : 7; /*reg_clk_xtal_freq*/
uint32_t reg_clk_div_en : 1; /*reg_clk_div_en*/
uint32_t reserved20 : 12; /*reserved*/
};
uint32_t val;
} sysclk_conf;
union {
struct {
uint32_t reg_mem_path_len : 4; /*reg_mem_path_len*/
@@ -296,120 +158,28 @@ typedef volatile struct {
};
uint32_t val;
} mem_pvt;
union {
struct {
uint32_t reg_comb_path_len_lvt : 5; /*reg_comb_path_len_lvt*/
uint32_t reg_comb_err_cnt_clr_lvt : 1; /*reg_comb_err_cnt_clr_lvt*/
uint32_t reg_comb_pvt_monitor_en_lvt : 1; /*reg_comb_pvt_monitor_en_lvt*/
uint32_t reserved7 : 18; /*reserved*/
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} comb_pvt_lvt_conf;
union {
struct {
uint32_t reg_comb_path_len_nvt : 5; /*reg_comb_path_len_nvt*/
uint32_t reg_comb_err_cnt_clr_nvt : 1; /*reg_comb_err_cnt_clr_nvt*/
uint32_t reg_comb_pvt_monitor_en_nvt : 1; /*reg_comb_pvt_monitor_en_nvt*/
uint32_t reserved7 : 18; /*reserved*/
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} comb_pvt_nvt_conf;
union {
struct {
uint32_t reg_comb_path_len_hvt : 5; /*reg_comb_path_len_hvt*/
uint32_t reg_comb_err_cnt_clr_hvt : 1; /*reg_comb_err_cnt_clr_hvt*/
uint32_t reg_comb_pvt_monitor_en_hvt : 1; /*reg_comb_pvt_monitor_en_hvt*/
uint32_t reserved7 : 18; /*reserved*/
uint32_t reserved25 : 7; /*reserved*/
};
uint32_t val;
} comb_pvt_hvt_conf;
union {
struct {
uint32_t reg_comb_timing_err_cnt_lvt_site0: 16; /*reg_comb_timing_err_cnt_lvt_site0*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_lvt_site0;
union {
struct {
uint32_t reg_comb_timing_err_cnt_nvt_site0: 16; /*reg_comb_timing_err_cnt_nvt_site0*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_nvt_site0;
union {
struct {
uint32_t reg_comb_timing_err_cnt_hvt_site0: 16; /*reg_comb_timing_err_cnt_hvt_site0*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_hvt_site0;
union {
struct {
uint32_t reg_comb_timing_err_cnt_lvt_site1: 16; /*reg_comb_timing_err_cnt_lvt_site1*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_lvt_site1;
union {
struct {
uint32_t reg_comb_timing_err_cnt_nvt_site1: 16; /*reg_comb_timing_err_cnt_nvt_site1*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_nvt_site1;
union {
struct {
uint32_t reg_comb_timing_err_cnt_hvt_site1: 16; /*reg_comb_timing_err_cnt_hvt_site1*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_hvt_site1;
union {
struct {
uint32_t reg_comb_timing_err_cnt_lvt_site2: 16; /*reg_comb_timing_err_cnt_lvt_site2*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_lvt_site2;
union {
struct {
uint32_t reg_comb_timing_err_cnt_nvt_site2: 16; /*reg_comb_timing_err_cnt_nvt_site2*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_nvt_site2;
union {
struct {
uint32_t reg_comb_timing_err_cnt_hvt_site2: 16; /*reg_comb_timing_err_cnt_hvt_site2*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_hvt_site2;
union {
struct {
uint32_t reg_comb_timing_err_cnt_lvt_site3: 16; /*reg_comb_timing_err_cnt_lvt_site3*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_lvt_site3;
union {
struct {
uint32_t reg_comb_timing_err_cnt_nvt_site3: 16; /*reg_comb_timing_err_cnt_nvt_site3*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_nvt_site3;
union {
struct {
uint32_t reg_comb_timing_err_cnt_hvt_site3: 16; /*reg_comb_timing_err_cnt_hvt_site3*/
uint32_t reserved16 : 16; /*reserved*/
};
uint32_t val;
} comb_pvt_err_hvt_site3;
uint32_t reserved_44;
uint32_t reserved_48;
uint32_t reserved_4c;
uint32_t reserved_50;
uint32_t reserved_54;
uint32_t reserved_58;
uint32_t reserved_5c;
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
uint32_t reserved_80;
uint32_t reserved_84;
uint32_t reserved_88;
uint32_t reserved_8c;
uint32_t reserved_90;
uint32_t reserved_94;
uint32_t reserved_98;
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;

917
components/soc/esp32h2/include/soc/systimer_reg.h
View File

@@ -1,567 +1,424 @@
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#pragma once
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SYS_TIMER_REG_H_
#define _SOC_SYS_TIMER_REG_H_
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000)
/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: register file clk gating*/
#define SYS_TIMER_CLK_EN (BIT(31))
#define SYS_TIMER_CLK_EN_M (BIT(31))
#define SYS_TIMER_CLK_EN_V 0x1
#define SYS_TIMER_CLK_EN_S 31
/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
/*description: timer unit0 work enable*/
#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30
/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer unit1 work enable*/
#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29
/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core0 stalled*/
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28))
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
/*description: If timer unit0 is stalled when core1 stalled*/
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27))
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core0 stalled*/
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26))
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
/*description: If timer unit1 is stalled when core1 stalled*/
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25))
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1
#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
/*description: target0 work enable*/
#define SYS_TIMER_TARGET0_WORK_EN (BIT(24))
#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24))
#define SYS_TIMER_TARGET0_WORK_EN_V 0x1
#define SYS_TIMER_TARGET0_WORK_EN_S 24
/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: target1 work enable*/
#define SYS_TIMER_TARGET1_WORK_EN (BIT(23))
#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23))
#define SYS_TIMER_TARGET1_WORK_EN_V 0x1
#define SYS_TIMER_TARGET1_WORK_EN_S 23
/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: target2 work enable*/
#define SYS_TIMER_TARGET2_WORK_EN (BIT(22))
#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22))
#define SYS_TIMER_TARGET2_WORK_EN_V 0x1
#define SYS_TIMER_TARGET2_WORK_EN_S 22
/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: systimer clock force on*/
#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0))
#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0))
#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1
#define SYS_TIMER_SYSTIMER_CLK_FO_S 0
/** SYSTIMER_CONF_REG register
* SYSTIMER_CONF.
*/
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
* systimer clock force on
*/
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
* target2 work enable
*/
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET2_WORK_EN_S 22
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
* target1 work enable
*/
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET1_WORK_EN_S 23
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
* target0 work enable
*/
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001
#define SYSTIMER_TARGET0_WORK_EN_S 24
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
* If timer unit1 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
* If timer unit1 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
* If timer unit0 is stalled when core1 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
* If timer unit0 is stalled when core0 stalled
*/
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
* timer unit1 work enable
*/
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
* timer unit0 work enable
*/
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
* register file clk gating
*/
#define SYSTIMER_CLK_EN (BIT(31))
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
#define SYSTIMER_CLK_EN_V 0x00000001
#define SYSTIMER_CLK_EN_S 31
#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004)
/* SYS_TIMER_TIMER_UNIT0_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer_unit0*/
#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1
#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30
/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1
#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29
/** SYSTIMER_UNIT0_OP_REG register
* SYSTIMER_UNIT0_OP.
*/
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* reg_timer_unit0_value_valid
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
* update timer_unit0
*/
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008)
/* SYS_TIMER_TIMER_UNIT1_UPDATE : WT ;bitpos:[30] ;default: 1'b0 ; */
/*description: update timer unit1*/
#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30))
#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1
#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30
/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
/*description: timer value is sync and valid*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29))
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1
#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29
/** SYSTIMER_UNIT1_OP_REG register
* SYSTIMER_UNIT1_OP.
*/
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
* timer value is sync and valid
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
* update timer unit1
*/
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C)
/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit0 load high 32 bit*/
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_HI_S))
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0
/** SYSTIMER_UNIT0_LOAD_HI_REG register
* SYSTIMER_UNIT0_LOAD_HI.
*/
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit0 load high 32 bit
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010)
/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit0 load low 32 bit*/
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT0_LOAD_LO_S))
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0
/** SYSTIMER_UNIT0_LOAD_LO_REG register
* SYSTIMER_UNIT0_LOAD_LO.
*/
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit0 load low 32 bit
*/
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014)
/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer unit1 load high 32 bit*/
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_HI_S))
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0
/** SYSTIMER_UNIT1_LOAD_HI_REG register
* SYSTIMER_UNIT1_LOAD_HI.
*/
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
* timer unit1 load high 32 bit
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018)
/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer unit1 load low 32 bit*/
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V)<<(SYS_TIMER_TIMER_UNIT1_LOAD_LO_S))
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0
/** SYSTIMER_UNIT1_LOAD_LO_REG register
* SYSTIMER_UNIT1_LOAD_LO.
*/
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
* timer unit1 load low 32 bit
*/
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C)
/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget0 high 32 bit*/
#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V)<<(SYS_TIMER_TIMER_TARGET0_HI_S))
#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET0_HI_S 0
/** SYSTIMER_TARGET0_HI_REG register
* SYSTIMER_TARGET0_HI.
*/
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget0 high 32 bit
*/
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_TARGET0_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020)
/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget0 low 32 bit*/
#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V)<<(SYS_TIMER_TIMER_TARGET0_LO_S))
#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET0_LO_S 0
/** SYSTIMER_TARGET0_LO_REG register
* SYSTIMER_TARGET0_LO.
*/
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget0 low 32 bit
*/
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET0_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024)
/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget1 high 32 bit*/
#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V)<<(SYS_TIMER_TIMER_TARGET1_HI_S))
#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET1_HI_S 0
/** SYSTIMER_TARGET1_HI_REG register
* SYSTIMER_TARGET1_HI.
*/
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget1 high 32 bit
*/
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_TARGET1_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028)
/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget1 low 32 bit*/
#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V)<<(SYS_TIMER_TIMER_TARGET1_LO_S))
#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET1_LO_S 0
/** SYSTIMER_TARGET1_LO_REG register
* SYSTIMER_TARGET1_LO.
*/
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget1 low 32 bit
*/
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET1_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C)
/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer taget2 high 32 bit*/
#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF
#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V)<<(SYS_TIMER_TIMER_TARGET2_HI_S))
#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_TARGET2_HI_S 0
/** SYSTIMER_TARGET2_HI_REG register
* SYSTIMER_TARGET2_HI.
*/
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
* timer taget2 high 32 bit
*/
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_TARGET2_HI_S 0
#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030)
/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer taget2 low 32 bit*/
#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V)<<(SYS_TIMER_TIMER_TARGET2_LO_S))
#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_TARGET2_LO_S 0
/** SYSTIMER_TARGET2_LO_REG register
* SYSTIMER_TARGET2_LO.
*/
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
* timer taget2 low 32 bit
*/
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_TARGET2_LO_S 0
#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034)
/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target0 to period mode*/
#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target0 period*/
#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V)<<(SYS_TIMER_TARGET0_PERIOD_S))
#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET0_PERIOD_S 0
/** SYSTIMER_TARGET0_CONF_REG register
* SYSTIMER_TARGET0_CONF.
*/
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target0 period
*/
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF
#define SYSTIMER_TARGET0_PERIOD_S 0
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target0 to period mode
*/
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038)
/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target1 to period mode*/
#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target1 period*/
#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V)<<(SYS_TIMER_TARGET1_PERIOD_S))
#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET1_PERIOD_S 0
/** SYSTIMER_TARGET1_CONF_REG register
* SYSTIMER_TARGET1_CONF.
*/
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target1 period
*/
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF
#define SYSTIMER_TARGET1_PERIOD_S 0
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target1 to period mode
*/
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C)
/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: select which unit to compare*/
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31))
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1
#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31
/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
/*description: Set target2 to period mode*/
#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30))
#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1
#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30
/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
/*description: target2 period*/
#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF
#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V)<<(SYS_TIMER_TARGET2_PERIOD_S))
#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF
#define SYS_TIMER_TARGET2_PERIOD_S 0
/** SYSTIMER_TARGET2_CONF_REG register
* SYSTIMER_TARGET2_CONF.
*/
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
* target2 period
*/
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF
#define SYSTIMER_TARGET2_PERIOD_S 0
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
* Set target2 to period mode
*/
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
* select which unit to compare
*/
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040)
/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 32bit*/
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_HI_S))
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0
/** SYSTIMER_UNIT0_VALUE_HI_REG register
* SYSTIMER_UNIT0_VALUE_HI.
*/
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 32bit
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044)
/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bit*/
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT0_VALUE_LO_S))
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0
/** SYSTIMER_UNIT0_VALUE_LO_REG register
* SYSTIMER_UNIT0_VALUE_LO.
*/
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bit
*/
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048)
/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */
/*description: timer read value high 32bit*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_HI_S))
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0
/** SYSTIMER_UNIT1_VALUE_HI_REG register
* SYSTIMER_UNIT1_VALUE_HI.
*/
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
* timer read value high 32bit
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C)
/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */
/*description: timer read value low 32bit*/
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V)<<(SYS_TIMER_TIMER_UNIT1_VALUE_LO_S))
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0
/** SYSTIMER_UNIT1_VALUE_LO_REG register
* SYSTIMER_UNIT1_VALUE_LO.
*/
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
* timer read value low 32bit
*/
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050)
/* SYS_TIMER_TIMER_COMP0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp0 load value*/
#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP0_LOAD_S 0
/** SYSTIMER_COMP0_LOAD_REG register
* SYSTIMER_COMP0_LOAD.
*/
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
* timer comp0 load value
*/
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054)
/* SYS_TIMER_TIMER_COMP1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp1 load value*/
#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP1_LOAD_S 0
/** SYSTIMER_COMP1_LOAD_REG register
* SYSTIMER_COMP1_LOAD.
*/
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
* timer comp1 load value
*/
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058)
/* SYS_TIMER_TIMER_COMP2_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer comp2 load value*/
#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1
#define SYS_TIMER_TIMER_COMP2_LOAD_S 0
/** SYSTIMER_COMP2_LOAD_REG register
* SYSTIMER_COMP2_LOAD.
*/
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
* timer comp2 load value
*/
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C)
/* SYS_TIMER_TIMER_UNIT0_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit0 load value*/
#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1
#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0
/** SYSTIMER_UNIT0_LOAD_REG register
* SYSTIMER_UNIT0_LOAD.
*/
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
* timer unit0 load value
*/
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060)
/* SYS_TIMER_TIMER_UNIT1_LOAD : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: timer unit1 load value*/
#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0))
#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1
#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0
/** SYSTIMER_UNIT1_LOAD_REG register
* SYSTIMER_UNIT1_LOAD.
*/
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
* timer unit1 load value
*/
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064)
/* SYS_TIMER_TARGET2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 enable*/
#define SYS_TIMER_TARGET2_INT_ENA (BIT(2))
#define SYS_TIMER_TARGET2_INT_ENA_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_ENA_V 0x1
#define SYS_TIMER_TARGET2_INT_ENA_S 2
/* SYS_TIMER_TARGET1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 enable*/
#define SYS_TIMER_TARGET1_INT_ENA (BIT(1))
#define SYS_TIMER_TARGET1_INT_ENA_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_ENA_V 0x1
#define SYS_TIMER_TARGET1_INT_ENA_S 1
/* SYS_TIMER_TARGET0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 enable*/
#define SYS_TIMER_TARGET0_INT_ENA (BIT(0))
#define SYS_TIMER_TARGET0_INT_ENA_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_ENA_V 0x1
#define SYS_TIMER_TARGET0_INT_ENA_S 0
/** SYSTIMER_INT_ENA_REG register
* SYSTIMER_INT_ENA.
*/
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
* interupt0 enable
*/
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET0_INT_ENA_S 0
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
* interupt1 enable
*/
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET1_INT_ENA_S 1
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
* interupt2 enable
*/
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001
#define SYSTIMER_TARGET2_INT_ENA_S 2
#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068)
/* SYS_TIMER_TARGET2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 raw*/
#define SYS_TIMER_TARGET2_INT_RAW (BIT(2))
#define SYS_TIMER_TARGET2_INT_RAW_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_RAW_V 0x1
#define SYS_TIMER_TARGET2_INT_RAW_S 2
/* SYS_TIMER_TARGET1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 raw*/
#define SYS_TIMER_TARGET1_INT_RAW (BIT(1))
#define SYS_TIMER_TARGET1_INT_RAW_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_RAW_V 0x1
#define SYS_TIMER_TARGET1_INT_RAW_S 1
/* SYS_TIMER_TARGET0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 raw*/
#define SYS_TIMER_TARGET0_INT_RAW (BIT(0))
#define SYS_TIMER_TARGET0_INT_RAW_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_RAW_V 0x1
#define SYS_TIMER_TARGET0_INT_RAW_S 0
/** SYSTIMER_INT_RAW_REG register
* SYSTIMER_INT_RAW.
*/
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* interupt0 raw
*/
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET0_INT_RAW_S 0
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
* interupt1 raw
*/
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET1_INT_RAW_S 1
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
* interupt2 raw
*/
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001
#define SYSTIMER_TARGET2_INT_RAW_S 2
#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c)
/* SYS_TIMER_TARGET2_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
/*description: interupt2 clear*/
#define SYS_TIMER_TARGET2_INT_CLR (BIT(2))
#define SYS_TIMER_TARGET2_INT_CLR_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_CLR_V 0x1
#define SYS_TIMER_TARGET2_INT_CLR_S 2
/* SYS_TIMER_TARGET1_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: interupt1 clear*/
#define SYS_TIMER_TARGET1_INT_CLR (BIT(1))
#define SYS_TIMER_TARGET1_INT_CLR_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_CLR_V 0x1
#define SYS_TIMER_TARGET1_INT_CLR_S 1
/* SYS_TIMER_TARGET0_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: interupt0 clear*/
#define SYS_TIMER_TARGET0_INT_CLR (BIT(0))
#define SYS_TIMER_TARGET0_INT_CLR_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_CLR_V 0x1
#define SYS_TIMER_TARGET0_INT_CLR_S 0
/** SYSTIMER_INT_CLR_REG register
* SYSTIMER_INT_CLR.
*/
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
* interupt0 clear
*/
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET0_INT_CLR_S 0
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
* interupt1 clear
*/
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET1_INT_CLR_S 1
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
* interupt2 clear
*/
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001
#define SYSTIMER_TARGET2_INT_CLR_S 2
#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070)
/* SYS_TIMER_TARGET2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TARGET2_INT_ST (BIT(2))
#define SYS_TIMER_TARGET2_INT_ST_M (BIT(2))
#define SYS_TIMER_TARGET2_INT_ST_V 0x1
#define SYS_TIMER_TARGET2_INT_ST_S 2
/* SYS_TIMER_TARGET1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TARGET1_INT_ST (BIT(1))
#define SYS_TIMER_TARGET1_INT_ST_M (BIT(1))
#define SYS_TIMER_TARGET1_INT_ST_V 0x1
#define SYS_TIMER_TARGET1_INT_ST_S 1
/* SYS_TIMER_TARGET0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
#define SYS_TIMER_TARGET0_INT_ST (BIT(0))
#define SYS_TIMER_TARGET0_INT_ST_M (BIT(0))
#define SYS_TIMER_TARGET0_INT_ST_V 0x1
#define SYS_TIMER_TARGET0_INT_ST_S 0
/** SYSTIMER_INT_ST_REG register
* SYSTIMER_INT_ST.
*/
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
* reg_target0_int_st
*/
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001
#define SYSTIMER_TARGET0_INT_ST_S 0
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
* reg_target1_int_st
*/
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001
#define SYSTIMER_TARGET1_INT_ST_S 1
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
* reg_target2_int_st
*/
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001
#define SYSTIMER_TARGET2_INT_ST_S 2
/** SYSTIMER_DATE_REG register
* SYSTIMER_DATE.
*/
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377;
* reg_date
*/
#define SYSTIMER_DATE 0xFFFFFFFF
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
#define SYSTIMER_DATE_V 0xFFFFFFFF
#define SYSTIMER_DATE_S 0
#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc)
/* SYS_TIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2006171 ; */
/*description: */
#define SYS_TIMER_DATE 0xFFFFFFFF
#define SYS_TIMER_DATE_M ((SYS_TIMER_DATE_V)<<(SYS_TIMER_DATE_S))
#define SYS_TIMER_DATE_V 0xFFFFFFFF
#define SYS_TIMER_DATE_S 0
#ifdef __cplusplus
}
#endif
#endif /*_SOC_SYS_TIMER_REG_H_ */

5
components/soc/esp32h2/include/soc/timer_group_reg.h
View File

@@ -37,6 +37,11 @@ extern "C" {
#define TIMG_WDT_RESET_LENGTH_800_NS 5
#define TIMG_WDT_RESET_LENGTH_1600_NS 6
#define TIMG_WDT_RESET_LENGTH_3200_NS 7
/* Possible values for TIMG_WDT_STGx */
#define TIMG_WDT_STG_SEL_OFF 0
#define TIMG_WDT_STG_SEL_INT 1
#define TIMG_WDT_STG_SEL_RESET_CPU 2
#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000)
/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */

2
components/soc/esp32h2/include/soc/twai_struct.h
View File

@@ -22,7 +22,7 @@ extern "C" {
/* ---------------------------- Register Layout ------------------------------ */
/* The TWAI peripheral's registers are 8bits, however the ESP32-C3 can only access
/* The TWAI peripheral's registers are 8bits, however the ESP32-H2 can only access
* peripheral registers every 32bits. Therefore each TWAI register is mapped to
* the least significant byte of every 32bits.
*/

2
components/soc/esp32h2/soc_memory_layout.c
View File

@@ -91,7 +91,7 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
/* We use _rtc_force_slow_end not _rtc_noinit_end here, as rtc "fast" memory ends up in RTC SLOW
region on C3, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections.
region on H2, no differentiation. And _rtc_force_slow_end is the end of all the static RTC sections.
*/
SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
#endif