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change(gpio): esp32p4 available pins are GPIO0 ~ GPIO54

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Song Ruo Jing
2023-12-19 22:31:14 +08:00
parent 88cc473910
commit 20f6505aa6
12 changed files with 34 additions and 68 deletions
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12
docs/en/api-reference/peripherals/gpio/esp32p4.inc
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@@ -9,7 +9,7 @@
.. gpio-summary
The {IDF_TARGET_NAME} chip features 57 physical GPIO pins (GPIO0 ~ GPIO56). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The {IDF_TARGET_NAME} chip features 55 physical GPIO pins (GPIO0 ~ GPIO54). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
@@ -297,16 +297,6 @@ The table below provides more information on pin usage, and please note the comm
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* - GPIO55
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* - GPIO56
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.. note::
- Strapping pin: GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 are strapping pins. For more infomation, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.