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apptrace: Adds ESP32-C3 support

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This commit is contained in:
Alexey Gerenkov
2021-05-29 00:20:02 +03:00
parent 821869d98d
commit 20fd09728f
8 changed files with 427 additions and 18 deletions
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32
components/soc/esp32c3/interrupts.c
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@@ -14,9 +14,9 @@
#include "soc/interrupts.h"
const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
const char *const esp_isr_names[] = {
[0] = "WIFI_MAC",
[1] = "WIFI_NMI",
[1] = "WIFI_MAC_NMI",
[2] = "WIFI_PWR",
[3] = "WIFI_BB",
[4] = "BT_MAC",
@@ -26,7 +26,7 @@ const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
[8] = "RWBLE",
[9] = "RWBT_NMI",
[10] = "RWBLE_NMI",
[11] = "I2C",
[11] = "I2C_MASTER",
[12] = "SLC0",
[13] = "SLC1",
[14] = "APB_CTRL",
@@ -40,7 +40,7 @@ const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
[22] = "UART1",
[23] = "LEDC",
[24] = "EFUSE",
[25] = "CAN",
[25] = "TWAI",
[26] = "USB",
[27] = "RTC_CORE",
[28] = "RMT",
@@ -65,16 +65,16 @@ const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
[47] = "RSA",
[48] = "AES",
[49] = "SHA",
[50] = "ETS_FROM_CPU_INTR0",
[51] = "ETS_FROM_CPU_INTR1",
[52] = "ETS_FROM_CPU_INTR2",
[53] = "ETS_FROM_CPU_INTR3",
[54] = "ETS_ASSIST_DEBUG",
[55] = "ETS_DMA_APBPERI_PMS",
[56] = "ETS_CORE0_IRAM0_PMS",
[57] = "ETS_CORE0_DRAM0_PMS",
[58] = "ETS_CORE0_PIF_PMS",
[59] = "ETS_CORE0_PIF_PMS_SIZE",
[60] = "ETS_BAK_PMS_VIOLATE",
[61] = "ETS_CACHE_CORE0_ACS",
[50] = "FROM_CPU_INTR0",
[51] = "FROM_CPU_INTR1",
[52] = "FROM_CPU_INTR2",
[53] = "FROM_CPU_INTR3",
[54] = "ASSIST_DEBUG",
[55] = "DMA_APBPERI_PMS",
[56] = "CORE0_IRAM0_PMS",
[57] = "CORE0_DRAM0_PMS",
[58] = "CORE0_PIF_PMS",
[59] = "CORE0_PIF_PMS_SIZE",
[60] = "BAK_PMS_VIOLATE",
[61] = "CACHE_CORE0_ACS",
};