From 2292bd6473bc9fddea234bdea2cc2cc591457dfd Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Tue, 22 Jul 2025 12:17:31 +0800 Subject: [PATCH] fix(lp_io): w1ts/w1tc register access performance is improved by avoiding "read-modify-write" operation. The registers designed to be write only. --- components/hal/esp32/include/hal/rtc_io_ll.h | 8 ++++---- components/hal/esp32c5/include/hal/rtc_io_ll.h | 10 +++++----- components/hal/esp32c6/include/hal/rtc_io_ll.h | 10 +++++----- components/hal/esp32c61/include/hal/rtc_io_ll.h | 10 +++++----- components/hal/esp32p4/include/hal/rtc_io_ll.h | 10 +++++----- components/hal/esp32s2/include/hal/rtc_io_ll.h | 8 ++++---- components/hal/esp32s3/include/hal/rtc_io_ll.h | 8 ++++---- 7 files changed, 32 insertions(+), 32 deletions(-) diff --git a/components/hal/esp32/include/hal/rtc_io_ll.h b/components/hal/esp32/include/hal/rtc_io_ll.h index db1f8a8654..7b0fef6b1c 100644 --- a/components/hal/esp32/include/hal/rtc_io_ll.h +++ b/components/hal/esp32/include/hal/rtc_io_ll.h @@ -73,7 +73,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); + RTCIO.enable_w1ts.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TS_S)); } /** @@ -83,7 +83,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); + RTCIO.enable_w1tc.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TC_S)); } /** @@ -95,9 +95,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - RTCIO.out_w1ts.w1ts = (1U << rtcio_num); + RTCIO.out_w1ts.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TS_S)); } else { - RTCIO.out_w1tc.w1tc = (1U << rtcio_num); + RTCIO.out_w1tc.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TC_S)); } } diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/hal/esp32c5/include/hal/rtc_io_ll.h index cae63b9642..14695bb6a9 100644 --- a/components/hal/esp32c5/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c5/include/hal/rtc_io_ll.h @@ -102,7 +102,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num); + LP_GPIO.enable_w1ts.val = BIT(rtcio_num); } /** @@ -112,7 +112,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num); + LP_GPIO.enable_w1tc.val = BIT(rtcio_num); } /** @@ -124,9 +124,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num); + LP_GPIO.out_w1ts.val = BIT(rtcio_num); } else { - LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num); + LP_GPIO.out_w1tc.val = BIT(rtcio_num); } } @@ -437,7 +437,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void) */ static inline void rtcio_ll_clear_interrupt_status(void) { - LP_GPIO.status_w1tc.status_w1tc = 0x7F; + LP_GPIO.status_w1tc.val = 0x7F; } #ifdef __cplusplus diff --git a/components/hal/esp32c6/include/hal/rtc_io_ll.h b/components/hal/esp32c6/include/hal/rtc_io_ll.h index 708e53108a..b50b3590b8 100644 --- a/components/hal/esp32c6/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c6/include/hal/rtc_io_ll.h @@ -100,7 +100,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1ts, enable_w1ts, BIT(rtcio_num)); + LP_IO.out_enable_w1ts.val = BIT(rtcio_num); } /** @@ -110,7 +110,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_enable_w1tc, enable_w1tc, BIT(rtcio_num)); + LP_IO.out_enable_w1tc.val = BIT(rtcio_num); } /** @@ -122,9 +122,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1ts, out_w1ts, BIT(rtcio_num)); + LP_IO.out_data_w1ts.val = BIT(rtcio_num); } else { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.out_data_w1tc, out_w1tc, BIT(rtcio_num)); + LP_IO.out_data_w1tc.val = BIT(rtcio_num); } } @@ -443,7 +443,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void) */ static inline void rtcio_ll_clear_interrupt_status(void) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_IO.status_w1tc, status_intr_w1tc, 0xff); + LP_IO.status_w1tc.val = 0xFF; } #ifdef __cplusplus diff --git a/components/hal/esp32c61/include/hal/rtc_io_ll.h b/components/hal/esp32c61/include/hal/rtc_io_ll.h index d5b6001513..46b1a601be 100644 --- a/components/hal/esp32c61/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c61/include/hal/rtc_io_ll.h @@ -101,7 +101,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - LP_GPIO.enable_w1ts.enable_w1ts = BIT(rtcio_num); + LP_GPIO.enable_w1ts.val = BIT(rtcio_num); } /** @@ -111,7 +111,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - LP_GPIO.enable_w1tc.enable_w1tc = BIT(rtcio_num); + LP_GPIO.enable_w1tc.val = BIT(rtcio_num); } /** @@ -123,9 +123,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - LP_GPIO.out_w1ts.out_w1ts = BIT(rtcio_num); + LP_GPIO.out_w1ts.val = BIT(rtcio_num); } else { - LP_GPIO.out_w1tc.out_w1tc = BIT(rtcio_num); + LP_GPIO.out_w1tc.val = BIT(rtcio_num); } } @@ -436,7 +436,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void) */ static inline void rtcio_ll_clear_interrupt_status(void) { - LP_GPIO.status_w1tc.status_w1tc = 0x7F; + LP_GPIO.status_w1tc.val = 0x7F; } #ifdef __cplusplus diff --git a/components/hal/esp32p4/include/hal/rtc_io_ll.h b/components/hal/esp32p4/include/hal/rtc_io_ll.h index e0d56fd658..f1261cae44 100644 --- a/components/hal/esp32p4/include/hal/rtc_io_ll.h +++ b/components/hal/esp32p4/include/hal/rtc_io_ll.h @@ -134,7 +134,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1ts, reg_gpio_enable_data_w1ts, BIT(rtcio_num)); + LP_GPIO.enable_w1ts.val = BIT(rtcio_num); } /** @@ -144,7 +144,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.enable_w1tc, reg_gpio_enable_data_w1tc, BIT(rtcio_num)); + LP_GPIO.enable_w1tc.val = BIT(rtcio_num); // Ensure no other output signal is routed via LP_GPIO matrix to this pin LP_GPIO.func_out_sel_cfg[rtcio_num].func_out_sel = SIG_LP_GPIO_OUT_IDX; } @@ -158,9 +158,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1ts, reg_gpio_out_data_w1ts, BIT(rtcio_num)); + LP_GPIO.out_w1ts.val = BIT(rtcio_num); } else { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.out_w1tc, reg_gpio_out_data_w1tc, BIT(rtcio_num)); + LP_GPIO.out_w1tc.val = BIT(rtcio_num); } } @@ -471,7 +471,7 @@ static inline uint32_t rtcio_ll_get_interrupt_status(void) */ static inline void rtcio_ll_clear_interrupt_status(void) { - HAL_FORCE_MODIFY_U32_REG_FIELD(LP_GPIO.status_w1tc, reg_gpio_status_data_w1tc, 0xFFFF); + LP_GPIO.status_w1tc.val = 0xFFFF; } #ifdef __cplusplus diff --git a/components/hal/esp32s2/include/hal/rtc_io_ll.h b/components/hal/esp32s2/include/hal/rtc_io_ll.h index 2d4ae76de8..3a0ef83d0f 100644 --- a/components/hal/esp32s2/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_io_ll.h @@ -84,7 +84,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); + RTCIO.enable_w1ts.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TS_S)); } /** @@ -94,7 +94,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); + RTCIO.enable_w1tc.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TC_S)); } /** @@ -106,9 +106,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - RTCIO.out_w1ts.w1ts = (1U << rtcio_num); + RTCIO.out_w1ts.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TS_S)); } else { - RTCIO.out_w1tc.w1tc = (1U << rtcio_num); + RTCIO.out_w1tc.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TC_S)); } } diff --git a/components/hal/esp32s3/include/hal/rtc_io_ll.h b/components/hal/esp32s3/include/hal/rtc_io_ll.h index 00a9d75ce6..cdfa100aa0 100644 --- a/components/hal/esp32s3/include/hal/rtc_io_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_io_ll.h @@ -93,7 +93,7 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func) */ static inline void rtcio_ll_output_enable(int rtcio_num) { - RTCIO.enable_w1ts.w1ts = (1U << rtcio_num); + RTCIO.enable_w1ts.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TS_S)); } /** @@ -103,7 +103,7 @@ static inline void rtcio_ll_output_enable(int rtcio_num) */ static inline void rtcio_ll_output_disable(int rtcio_num) { - RTCIO.enable_w1tc.w1tc = (1U << rtcio_num); + RTCIO.enable_w1tc.val = (1U << (rtcio_num + RTC_GPIO_ENABLE_W1TC_S)); } /** @@ -115,9 +115,9 @@ static inline void rtcio_ll_output_disable(int rtcio_num) static inline void rtcio_ll_set_level(int rtcio_num, uint32_t level) { if (level) { - RTCIO.out_w1ts.w1ts = (1U << rtcio_num); + RTCIO.out_w1ts.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TS_S)); } else { - RTCIO.out_w1tc.w1tc = (1U << rtcio_num); + RTCIO.out_w1tc.val = (1U << (rtcio_num + RTC_GPIO_OUT_DATA_W1TC_S)); } }