alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-09 20:41:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feat/etm_driver_support_esp32c5' into 'master'

Browse Source 
feat(etm): support etm driver on esp32c5

Closes IDF-8693

See merge request espressif/esp-idf!32009
This commit is contained in:
morris
2024-07-15 18:05:49 +08:00
parent 2b351233cb 863344f769
commit 2386e522cb
34 changed files with 465 additions and 985 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -27,6 +27,10 @@ config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_ETM_SUPPORTED
bool
default y
config SOC_PARLIO_SUPPORTED
bool
default y
@@ -295,6 +299,18 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
int
default 3
config SOC_GDMA_SUPPORT_ETM
bool
default y
config SOC_ETM_GROUPS
int
default 1
config SOC_ETM_CHANNELS_PER_GROUP
int
default 50
config SOC_GPIO_PORT
int
default 1
@@ -307,6 +323,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
@@ -635,6 +655,10 @@ config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_ETM
bool
default y
config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
bool
default y
@@ -831,6 +855,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
bool
default y
config SOC_SYSTIMER_SUPPORT_ETM
bool
default y
config SOC_LP_TIMER_BIT_WIDTH_LO
int
default 32
@@ -855,10 +883,18 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TIMER_GROUP_SUPPORT_RC_FAST
bool
default y
config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_EFUSE_ECDSA_KEY
bool
default y

649
components/soc/esp32c5/include/soc/gpio_ext_struct.h
View File

@@ -192,20 +192,20 @@ typedef union {
* 28: Select GPIO28\\
* 29 ~ 63: Reserved\\
*/
uint32_t etm_ch0_event_sel:6;
uint32_t etm_chn_event_sel:6;
uint32_t reserved_6:1;
/** etm_ch0_event_en : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable ETM event send.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_ch0_event_en:1;
uint32_t etm_chn_event_en:1;
uint32_t reserved_8:24;
};
uint32_t val;
} gpio_ext_etm_event_chn_cfg_reg_t;
/** Type of etm_task_p0_cfg register
/** Type of etm_task_pn_cfg register
* GPIO selection register 0 for ETM
*/
typedef union {
@@ -333,633 +333,8 @@ typedef union {
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p0_cfg_reg_t;
} gpio_ext_etm_task_pn_cfg_reg_t;
/** Type of etm_task_p1_cfg register
* GPIO selection register 1 for ETM
*/
typedef union {
struct {
/** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio5_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio5_en:1;
/** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio6_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio6_en:1;
/** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio7_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio7_en:1;
/** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio8_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio8_en:1;
/** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio9_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio9_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p1_cfg_reg_t;
/** Type of etm_task_p2_cfg register
* GPIO selection register 2 for ETM
*/
typedef union {
struct {
/** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio10_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio10_en:1;
/** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio11_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio11_en:1;
/** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio12_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio12_en:1;
/** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio13_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio13_en:1;
/** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio14_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio14_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p2_cfg_reg_t;
/** Type of etm_task_p3_cfg register
* GPIO selection register 3 for ETM
*/
typedef union {
struct {
/** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio15_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio15_en:1;
/** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio16_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio16_en:1;
/** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio17_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio17_en:1;
/** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio18_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio18_en:1;
/** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio19_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio19_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p3_cfg_reg_t;
/** Type of etm_task_p4_cfg register
* GPIO selection register 4 for ETM
*/
typedef union {
struct {
/** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio20_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio20_en:1;
/** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio21_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio21_en:1;
/** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio22_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio22_en:1;
/** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio23_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio23_en:1;
/** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio24_sel:3;
uint32_t reserved_27:2;
/** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio24_en:1;
uint32_t reserved_30:2;
};
uint32_t val;
} gpio_ext_etm_task_p4_cfg_reg_t;
/** Type of etm_task_p5_cfg register
* GPIO selection register 5 for ETM
*/
typedef union {
struct {
/** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio25_sel:3;
uint32_t reserved_3:2;
/** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio25_en:1;
/** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio26_sel:3;
uint32_t reserved_9:2;
/** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio26_en:1;
/** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio27_sel:3;
uint32_t reserved_15:2;
/** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio27_en:1;
/** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0;
* Configures to select an ETM task channel for GPIO$n.\\
* 0: Select channel 0\\
* 1: Select channel 1\\
* ......\\
* 7: Select channel 7\\%\label{fielddesc:GPIOSDETMTASKGPIO1EN}-
* [GPIOSD_ETM_TASK_GPIO1_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO1SEL}- [GPIOSD_ETM_TASK_GPIO1_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO2EN}-
* [GPIOSD_ETM_TASK_GPIO2_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO2SEL}- [GPIOSD_ETM_TASK_GPIO2_SEL] GPIO choose a
* etm task channel. %\label{fielddesc:GPIOSDETMTASKGPIO3EN}\item
* [GPIOSD_ETM_TASK_GPIO3_EN] Enable bit of GPIO response etm task.
* %\label{fielddesc:GPIOSDETMTASKGPIO3SEL}\item [GPIOSD_ETM_TASK_GPIO3_SEL] GPIO
* choose a etm task channel.
*/
uint32_t etm_task_gpio28_sel:3;
uint32_t reserved_21:2;
/** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0;
* Configures whether or not to enable GPIO$n to response ETM task.\\
* 0: Not enable\\
* 1: Enable\\
*/
uint32_t etm_task_gpio28_en:1;
uint32_t reserved_24:8;
};
uint32_t val;
} gpio_ext_etm_task_p5_cfg_reg_t;
/** Group: Interrupt Registers */
@@ -1073,6 +448,12 @@ typedef struct gpio_sd_dev_t {
volatile gpio_ext_sigmadeltan_reg_t channel[4];
} gpio_sd_dev_t;
typedef struct gpio_etm_dev_t {
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_080[8];
volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[6];
} gpio_etm_dev_t;
typedef struct {
volatile gpio_sd_dev_t sigma_delta;
uint32_t reserved_018[16];
@@ -1081,14 +462,7 @@ typedef struct {
uint32_t reserved_060[30];
volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
uint32_t reserved_0f8[8];
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
uint32_t reserved_138[8];
volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
volatile gpio_ext_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
volatile gpio_etm_dev_t etm;
uint32_t reserved_170[24];
volatile gpio_ext_int_raw_reg_t int_raw;
volatile gpio_ext_int_st_reg_t int_st;
@@ -1100,6 +474,7 @@ typedef struct {
} gpio_ext_dev_t;
extern gpio_sd_dev_t SDM;
extern gpio_etm_dev_t GPIO_ETM;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus

18
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -26,7 +26,7 @@
#define SOC_PCNT_SUPPORTED 1
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693
#define SOC_ETM_SUPPORTED 1
#define SOC_PARLIO_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
@@ -177,12 +177,12 @@
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_NUM_GROUPS_MAX 1U
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9224
#define SOC_GDMA_SUPPORT_ETM 1
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-9225
/*-------------------------- ETM CAPS --------------------------------------*/
// #define SOC_ETM_GROUPS 1U // Number of ETM groups
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
#define SOC_ETM_GROUPS 1U // Number of ETM groups
#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C5 has 1 GPIO peripheral
@@ -193,7 +193,7 @@
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
#define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem
// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
@@ -338,7 +338,7 @@
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3 ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3 ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1 ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1 ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP 1 ///< Capture timer shares clock with other PWM timers
@@ -438,7 +438,7 @@
#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
@@ -449,9 +449,9 @@
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
// #define SOC_TIMER_SUPPORT_ETM (1)
#define SOC_TIMER_SUPPORT_ETM (1)
// #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/

106
components/soc/esp32c5/include/soc/soc_etm_struct.h
View File

@@ -3602,113 +3602,17 @@ typedef union {
} soc_etm_date_reg_t;
typedef struct {
typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
volatile soc_etm_chn_evt_id_reg_t ch0_evt_id;
volatile soc_etm_chn_task_id_reg_t ch0_task_id;
volatile soc_etm_chn_evt_id_reg_t ch1_evt_id;
volatile soc_etm_chn_task_id_reg_t ch1_task_id;
volatile soc_etm_chn_evt_id_reg_t ch2_evt_id;
volatile soc_etm_chn_task_id_reg_t ch2_task_id;
volatile soc_etm_chn_evt_id_reg_t ch3_evt_id;
volatile soc_etm_chn_task_id_reg_t ch3_task_id;
volatile soc_etm_chn_evt_id_reg_t ch4_evt_id;
volatile soc_etm_chn_task_id_reg_t ch4_task_id;
volatile soc_etm_chn_evt_id_reg_t ch5_evt_id;
volatile soc_etm_chn_task_id_reg_t ch5_task_id;
volatile soc_etm_chn_evt_id_reg_t ch6_evt_id;
volatile soc_etm_chn_task_id_reg_t ch6_task_id;
volatile soc_etm_chn_evt_id_reg_t ch7_evt_id;
volatile soc_etm_chn_task_id_reg_t ch7_task_id;
volatile soc_etm_chn_evt_id_reg_t ch8_evt_id;
volatile soc_etm_chn_task_id_reg_t ch8_task_id;
volatile soc_etm_chn_evt_id_reg_t ch9_evt_id;
volatile soc_etm_chn_task_id_reg_t ch9_task_id;
volatile soc_etm_chn_evt_id_reg_t ch10_evt_id;
volatile soc_etm_chn_task_id_reg_t ch10_task_id;
volatile soc_etm_chn_evt_id_reg_t ch11_evt_id;
volatile soc_etm_chn_task_id_reg_t ch11_task_id;
volatile soc_etm_chn_evt_id_reg_t ch12_evt_id;
volatile soc_etm_chn_task_id_reg_t ch12_task_id;
volatile soc_etm_chn_evt_id_reg_t ch13_evt_id;
volatile soc_etm_chn_task_id_reg_t ch13_task_id;
volatile soc_etm_chn_evt_id_reg_t ch14_evt_id;
volatile soc_etm_chn_task_id_reg_t ch14_task_id;
volatile soc_etm_chn_evt_id_reg_t ch15_evt_id;
volatile soc_etm_chn_task_id_reg_t ch15_task_id;
volatile soc_etm_chn_evt_id_reg_t ch16_evt_id;
volatile soc_etm_chn_task_id_reg_t ch16_task_id;
volatile soc_etm_chn_evt_id_reg_t ch17_evt_id;
volatile soc_etm_chn_task_id_reg_t ch17_task_id;
volatile soc_etm_chn_evt_id_reg_t ch18_evt_id;
volatile soc_etm_chn_task_id_reg_t ch18_task_id;
volatile soc_etm_chn_evt_id_reg_t ch19_evt_id;
volatile soc_etm_chn_task_id_reg_t ch19_task_id;
volatile soc_etm_chn_evt_id_reg_t ch20_evt_id;
volatile soc_etm_chn_task_id_reg_t ch20_task_id;
volatile soc_etm_chn_evt_id_reg_t ch21_evt_id;
volatile soc_etm_chn_task_id_reg_t ch21_task_id;
volatile soc_etm_chn_evt_id_reg_t ch22_evt_id;
volatile soc_etm_chn_task_id_reg_t ch22_task_id;
volatile soc_etm_chn_evt_id_reg_t ch23_evt_id;
volatile soc_etm_chn_task_id_reg_t ch23_task_id;
volatile soc_etm_chn_evt_id_reg_t ch24_evt_id;
volatile soc_etm_chn_task_id_reg_t ch24_task_id;
volatile soc_etm_chn_evt_id_reg_t ch25_evt_id;
volatile soc_etm_chn_task_id_reg_t ch25_task_id;
volatile soc_etm_chn_evt_id_reg_t ch26_evt_id;
volatile soc_etm_chn_task_id_reg_t ch26_task_id;
volatile soc_etm_chn_evt_id_reg_t ch27_evt_id;
volatile soc_etm_chn_task_id_reg_t ch27_task_id;
volatile soc_etm_chn_evt_id_reg_t ch28_evt_id;
volatile soc_etm_chn_task_id_reg_t ch28_task_id;
volatile soc_etm_chn_evt_id_reg_t ch29_evt_id;
volatile soc_etm_chn_task_id_reg_t ch29_task_id;
volatile soc_etm_chn_evt_id_reg_t ch30_evt_id;
volatile soc_etm_chn_task_id_reg_t ch30_task_id;
volatile soc_etm_chn_evt_id_reg_t ch31_evt_id;
volatile soc_etm_chn_task_id_reg_t ch31_task_id;
volatile soc_etm_chn_evt_id_reg_t ch32_evt_id;
volatile soc_etm_chn_task_id_reg_t ch32_task_id;
volatile soc_etm_chn_evt_id_reg_t ch33_evt_id;
volatile soc_etm_chn_task_id_reg_t ch33_task_id;
volatile soc_etm_chn_evt_id_reg_t ch34_evt_id;
volatile soc_etm_chn_task_id_reg_t ch34_task_id;
volatile soc_etm_chn_evt_id_reg_t ch35_evt_id;
volatile soc_etm_chn_task_id_reg_t ch35_task_id;
volatile soc_etm_chn_evt_id_reg_t ch36_evt_id;
volatile soc_etm_chn_task_id_reg_t ch36_task_id;
volatile soc_etm_chn_evt_id_reg_t ch37_evt_id;
volatile soc_etm_chn_task_id_reg_t ch37_task_id;
volatile soc_etm_chn_evt_id_reg_t ch38_evt_id;
volatile soc_etm_chn_task_id_reg_t ch38_task_id;
volatile soc_etm_chn_evt_id_reg_t ch39_evt_id;
volatile soc_etm_chn_task_id_reg_t ch39_task_id;
volatile soc_etm_chn_evt_id_reg_t ch40_evt_id;
volatile soc_etm_chn_task_id_reg_t ch40_task_id;
volatile soc_etm_chn_evt_id_reg_t ch41_evt_id;
volatile soc_etm_chn_task_id_reg_t ch41_task_id;
volatile soc_etm_chn_evt_id_reg_t ch42_evt_id;
volatile soc_etm_chn_task_id_reg_t ch42_task_id;
volatile soc_etm_chn_evt_id_reg_t ch43_evt_id;
volatile soc_etm_chn_task_id_reg_t ch43_task_id;
volatile soc_etm_chn_evt_id_reg_t ch44_evt_id;
volatile soc_etm_chn_task_id_reg_t ch44_task_id;
volatile soc_etm_chn_evt_id_reg_t ch45_evt_id;
volatile soc_etm_chn_task_id_reg_t ch45_task_id;
volatile soc_etm_chn_evt_id_reg_t ch46_evt_id;
volatile soc_etm_chn_task_id_reg_t ch46_task_id;
volatile soc_etm_chn_evt_id_reg_t ch47_evt_id;
volatile soc_etm_chn_task_id_reg_t ch47_task_id;
volatile soc_etm_chn_evt_id_reg_t ch48_evt_id;
volatile soc_etm_chn_task_id_reg_t ch48_task_id;
volatile soc_etm_chn_evt_id_reg_t ch49_evt_id;
volatile soc_etm_chn_task_id_reg_t ch49_task_id;
volatile struct {
soc_etm_chn_evt_id_reg_t eid;
soc_etm_chn_task_id_reg_t tid;
} channel[50];
volatile soc_etm_evt_st0_reg_t evt_st0;
volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
volatile soc_etm_evt_st1_reg_t evt_st1;

1
components/soc/esp32c5/ld/esp32c5.peripherals.ld
View File

@@ -44,6 +44,7 @@ PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091e00 );
PROVIDE ( SDM = 0x60091e00 );
PROVIDE ( GPIO_ETM = 0x60091f18 );
PROVIDE ( MEM_MONITOR = 0x60092000 );
PROVIDE ( PAU = 0x60093000 );
PROVIDE ( HP_SYSTEM = 0x60095000 );