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header files: modify rom code and soc header files

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1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
This commit is contained in:
jack
2016-08-31 21:53:23 +08:00
committed by Wu Jian Gang
parent fe3380d32e
commit 24011ddd05
19 changed files with 1944 additions and 737 deletions
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12
components/esp32/include/esp_intr.h
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@@ -61,8 +61,8 @@ extern "C" {
#define ESP_GPIO_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))
#define ESP_UART_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_UART_INUM, (func), (void *)(arg))
#define ESP_UART0_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))
#define ESP_WDT_INTR_ATTACH(func, arg) \
xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))
@@ -142,11 +142,11 @@ extern "C" {
#define ESP_BB_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_BB_INUM)
#define ESP_UART_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_UART_INUM)
#define ESP_UART0_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_UART0_INUM)
#define ESP_UART_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_UART_INUM)
#define ESP_UART0_INTR_DISABLE() \
ESP_INTR_DISABLE(ETS_UART0_INUM)
#define ESP_LEDC_INTR_ENABLE() \
ESP_INTR_ENABLE(ETS_LEDC_INUM)