header files: modify rom code and soc header files

1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions

components/esp32/include/rom/bigint.h

@@ -21,6 +21,7 @@
 extern "C" {
 #endif
 
+//TODO: add comment here
 void ets_bigint_enable(void);
 
 void ets_bigint_disable(void);