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header files: modify rom code and soc header files

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1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
This commit is contained in:
jack
2016-08-31 21:53:23 +08:00
committed by Wu Jian Gang
parent fe3380d32e
commit 24011ddd05
19 changed files with 1944 additions and 737 deletions
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30
components/esp32/include/soc/io_mux_reg.h
View File

@@ -80,21 +80,24 @@
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO25_U (DR_REG_IO_MUX_BASE +0x24)
#define FUNC_GPIO25_EMAC_RXD0 5
#define FUNC_GPIO25_GPIO25 2
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_GPIO26_U (DR_REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO26_EMAC_RXD1 5
#define FUNC_GPIO26_GPIO26 2
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_GPIO27_U (DR_REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO27_EMAC_RXD2 5
#define FUNC_GPIO27_EMAC_RX_DV 5
#define FUNC_GPIO27_GPIO27 2
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_MTMS_U (DR_REG_IO_MUX_BASE +0x30)
#define FUNC_MTMS_EMAC_TXD2 5
#define FUNC_MTMS_SD_CLK 4
#define FUNC_MTMS_HS2_CLk 3
#define FUNC_MTMS_GPIO14 2
#define FUNC_MTMS_HSPICLK 1
#define FUNC_MTMS_MTMS 0
@@ -102,6 +105,7 @@
#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
#define FUNC_MTDI_EMAC_TXD3 5
#define FUNC_MTDI_SD_DATA2 4
#define FUNC_MTDI_HS2_DATA2 3
#define FUNC_MTDI_GPIO12 2
#define FUNC_MTDI_HSPIQ 1
#define FUNC_MTDI_MTDI 0
@@ -109,7 +113,7 @@
#define PERIPHS_IO_MUX_MTCK_U (DR_REG_IO_MUX_BASE +0x38)
#define FUNC_MTCK_EMAC_RX_ER 5
#define FUNC_MTCK_SD_DATA3 4
#define FUNC_MTCK_U0CTS 3
#define FUNC_MTCK_HS2_DATA3 3
#define FUNC_MTCK_GPIO13 2
#define FUNC_MTCK_HSPID 1
#define FUNC_MTCK_MTCK 0
@@ -117,21 +121,20 @@
#define PERIPHS_IO_MUX_MTDO_U (DR_REG_IO_MUX_BASE +0x3c)
#define FUNC_MTDO_EMAC_RXD3 5
#define FUNC_MTDO_SD_CMD 4
#define FUNC_MTDO_U0RTS 3
#define FUNC_MTDO_HS2_CMD 3
#define FUNC_MTDO_GPIO15 2
#define FUNC_MTDO_HSPICS0 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_GPIO2_U (DR_REG_IO_MUX_BASE +0x40)
#define FUNC_GPIO2_EMAC_RX_DV 5
#define FUNC_GPIO2_SD_DATA0 4
#define FUNC_GPIO2_HS2_DATA0 3
#define FUNC_GPIO2_GPIO2 2
#define FUNC_GPIO2_HSPIWP 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO0_U (DR_REG_IO_MUX_BASE +0x44)
#define FUNC_GPIO0_EMAC_TX_CLK 5
#define FUNC_GPIO0_HS2_CMD 3
#define FUNC_GPIO0_GPIO0 2
#define FUNC_GPIO0_CLK_OUT1 1
#define FUNC_GPIO0_GPIO0_0 0
@@ -139,6 +142,7 @@
#define PERIPHS_IO_MUX_GPIO4_U (DR_REG_IO_MUX_BASE +0x48)
#define FUNC_GPIO4_EMAC_TX_ER 5
#define FUNC_GPIO4_SD_DATA1 4
#define FUNC_GPIO4_HS2_DATA1 3
#define FUNC_GPIO4_GPIO4 2
#define FUNC_GPIO4_HSPIHD 1
#define FUNC_GPIO4_GPIO4_0 0
@@ -207,15 +211,14 @@
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_GPIO18_U (DR_REG_IO_MUX_BASE +0x70)
#define FUNC_GPIO18_EMAC_TXD0 5
#define FUNC_GPIO18_HS1_DATA7 3
#define FUNC_GPIO18_GPIO18 2
#define FUNC_GPIO18_VSPICLK 1
#define FUNC_GPIO18_GPIO18_0 0
#define PERIPHS_IO_MUX_GPIO19_U (DR_REG_IO_MUX_BASE +0x74)
#define FUNC_GPIO19_EMAC_TXD1 5
#define FUNC_GPIO19_HS2_DATA2 3
#define FUNC_GPIO19_EMAC_TXD0 5
#define FUNC_GPIO19_U0CTS 3
#define FUNC_GPIO19_GPIO19 2
#define FUNC_GPIO19_VSPIQ 1
#define FUNC_GPIO19_GPIO19_0 0
@@ -225,33 +228,30 @@
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_GPIO21_U (DR_REG_IO_MUX_BASE +0x7c)
#define FUNC_GPIO21_EMAC_RXD0 5
#define FUNC_GPIO21_HS2_DATA3 3
#define FUNC_GPIO21_EMAC_TX_EN 5
#define FUNC_GPIO21_GPIO21 2
#define FUNC_GPIO21_VSPIHD 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_GPIO22_U (DR_REG_IO_MUX_BASE +0x80)
#define FUNC_GPIO22_EMAC_RXD1 5
#define FUNC_GPIO22_HS2_CLK 3
#define FUNC_GPIO22_EMAC_TXD1 5
#define FUNC_GPIO22_U0RTS 3
#define FUNC_GPIO22_GPIO22 2
#define FUNC_GPIO22_VSPIWP 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U0RXD_U (DR_REG_IO_MUX_BASE +0x84)
#define FUNC_U0RXD_HS2_DATA0 3
#define FUNC_U0RXD_GPIO3 2
#define FUNC_U0RXD_CLK_OUT2 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U0TXD_U (DR_REG_IO_MUX_BASE +0x88)
#define FUNC_U0TXD_HS2_DATA1 3
#define FUNC_U0TXD_EMAC_RXD2 3
#define FUNC_U0TXD_GPIO1 2
#define FUNC_U0TXD_CLK_OUT3 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_GPIO23_U (DR_REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO23_EMAC_TX_EN 5
#define FUNC_GPIO23_HS1_STROBE 3
#define FUNC_GPIO23_GPIO23 2
#define FUNC_GPIO23_VSPID 1

275
components/esp32/include/soc/soc.h
View File

@@ -61,10 +61,15 @@
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
//get bit or get bits
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
//set bit or set bits
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
//clear bit or clear bits
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
//set bits controll by mask
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
@@ -86,70 +91,25 @@
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM 13*1000000
#define APB_CLK_FREQ_ROM 26*1000000
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ 80*1000000 //unit: Hz
#define UART_CLK_FREQ APB_CLK_FREQ
//#define WDT_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16
#define SPI_CLK_DIV 4
//#define RTC_CLK_FREQ 32768 //unit:Hz
//#define RTC_CLK_FREQ 100000 //unit:Hz
//#define CALIB_CLK_MHZ 40
#define TICKS_PER_US 13 // CPU is 80MHz
#define TICKS_PER_US_ROM 26 // CPU is 80MHz
//}}
#if 0
//Peripheral device base address define{{
#define DR_REG_DPORT_BASE 0x3ff00000
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000 //no
#define DR_REG_SPI0_BASE 0x60003000 //no
#define DR_REG_GPIO_BASE 0x60004000 //no
#define DR_REG_FE2_BASE 0x60005000
#define DR_REG_FE_BASE 0x60006000
#define DR_REG_TIMER_BASE 0x60007000 //no
#define DR_REG_RTCCNTL_BASE 0x60008000
#define DR_REG_RTCIO_BASE 0x60008400
#define DR_REG_RTCMEM0_BASE 0x60021000
#define DR_REG_RTCMEM1_BASE 0x60022000
#define DR_REG_RTCMEM2_BASE 0x60023000
#define DR_REG_IO_MUX_BASE 0x60009000 //no
#define DR_REG_WDG_BASE 0x6000A000 //no
#define DR_REG_HINF_BASE 0x6000B000 //no
#define DR_REG_UHCI1_BASE 0x6000C000
//#define DR_REG_MISC_BASE 0x6000D000 //no use
#define DR_REG_I2C_BASE 0x6000E000 //no
#define DR_REG_I2S_BASE 0x6000F000
#define DR_REG_UART1_BASE 0x60010000
#define DR_REG_BT_BASE 0x60011000
//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use
#define DR_REG_I2C_EXT_BASE 0x60013000 //no
#define DR_REG_UHCI0_BASE 0x60014000
#define DR_REG_SLCHOST_BASE 0x60015000
#define DR_REG_RMT_BASE 0x60016000
#define DR_REG_PCNT_BASE 0x60017000
#define DR_REG_SLC_BASE 0x60018000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_EFUSE_BASE 0x6001A000
#define DR_REG_SPI_ENCRYPT_BASE 0x6001B000
#define DR_REG_PWM_BASE 0x6001C000 //no
#define DR_REG_TIMERGROUP_BASE 0x6001D000 //no
#define DR_REG_TIMERGROUP1_BASE 0x6001E000 //no
#define DR_REG_BB_BASE 0x6001F000
#define DR_REG_GPIO_SD_BASE 0x60004f00
#else
#define DR_REG_DPORT_BASE 0x3ff00000
#define DR_REG_UART_BASE 0x3ff40000
#define DR_REG_SPI1_BASE 0x3ff42000 //no
#define DR_REG_SPI0_BASE 0x3ff43000 //no
#define DR_REG_GPIO_BASE 0x3ff44000 //no
#define DR_REG_SPI1_BASE 0x3ff42000
#define DR_REG_SPI0_BASE 0x3ff43000
#define DR_REG_GPIO_BASE 0x3ff44000
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_TIMER_BASE 0x3ff47000 //no
#define DR_REG_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
@@ -157,18 +117,16 @@
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_IO_MUX_BASE 0x3ff49000 //no
#define DR_REG_WDG_BASE 0x3ff4A000 //no
#define DR_REG_HINF_BASE 0x3ff4B000 //no
#define DR_REG_IO_MUX_BASE 0x3ff49000
#define DR_REG_WDG_BASE 0x3ff4A000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
//#define DR_REG_MISC_BASE 0x6000D000 //no use
#define DR_REG_I2C_BASE 0x3ff4E000 //no
#define DR_REG_I2C_BASE 0x3ff4E000
#define DR_REG_I2S_BASE 0x3ff4F000
#define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
//#define DR_REG_BT_BUFFER_BASE 0x60012000 //no use
#define DR_REG_I2C_EXT_BASE 0x3ff53000 //no
#define DR_REG_I2C_EXT_BASE 0x3ff53000
#define DR_REG_UHCI0_BASE 0x3ff54000
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_RMT_BASE 0x3ff56000
@@ -177,94 +135,139 @@
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5A000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_PWM_BASE 0x3ff5C000 //no
#define DR_REG_TIMERS_BASE 0x3ff5F000 //no
#define DR_REG_TIMERGROUP1_BASE 0x3ff5E000 //no
#define DR_REG_BB_BASE 0x3ff5F000
#define DR_REG_BB_BASE 0x3ff5C000
#define DR_REG_PWM_BASE 0x3ff5E000
#define DR_REG_TIMERS_BASE(i) (0x3ff5F000 + i * (0x1000))
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#endif
//}}
#define REG_SPI_BASE(i) (DR_REG_SPI0_BASE - i*(0x1000))
#define PERIPHS_TIMER_BASEDDR DR_REG_TIMER_BASE
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
#define UART0_UNHOLD_MASK 0x3
#define UART1_UNHOLD_MASK 0x60
#define SDIO_UNHOLD_MASK 0xfc
#define SPI_UNHOLD_MASK 0xfc
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
#define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/
#define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
#define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/
#define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/
#define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/
#define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
#define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/
#define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/
#define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
#define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/
#define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/
#define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/
#define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/
#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/
#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/
#define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
#define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/
#define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/
#define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/
#define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/
#define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/
#define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/
#define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/
#define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/
#define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/
#define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/
#define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/
#define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/
#define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/
#define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/
#define ETS_CAN_INTR_SOURCE 45/**< interrupt of can, level*/
#define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/
#define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/
#define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/
#define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/
#define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/
#define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/
#define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/
#define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/
#define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/
#define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/
#define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/
#define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
#define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
#define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
#define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/
#define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/
#define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/
// TIMER reg {{
#define TIMER_REG_READ(addr) READ_PERI_REG(addr)
#define TIMER_REG_WRITE(addr, val) WRITE_PERI_REG(addr, val)
#define TIMER_SET_REG_MASK(reg, mask) WRITE_PERI_REG(reg, (READ_PERI_REG(reg)|(mask)))
/* Returns the current time according to the timer timer. */
#define NOW() TIMER_REG_READ(FRC2_COUNT_ADDRESS)
//load initial_value to timer1
#define FRC1_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR +0x00)
#define FRC1_LOAD_DATA_MSB 22
#define FRC1_LOAD_DATA_LSB 0
#define FRC1_LOAD_DATA_MASK 0x007fffff
//interrupt cpu using table, Please see the core-isa.h
/*************************************************************************************************************
* Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host Reserved
* 2 1 extern level FROM_CPU FROM_CPU
* 3 1 extern level TG0_WDT Reserved
* 4 1 extern level WBB
* 5 1 extern level Reserved
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
* 7 1 software Reserved Reserved
* 8 1 extern level Reserved
* 9 1 extern level
* 10 1 extern edge Internal Timer
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level
* 25 4 extern level Reserved Reserved
* 26 5 extern level Reserved Reserved
* 27 3 extern level Reserved Reserved
* 28 4 extern edge
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level Reserved Reserved
*************************************************************************************************************
*/
//timer1's counter value(count from initial_value to 0)
#define FRC1_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x04)
#define FRC1_COUNT_DATA_MSB 22
#define FRC1_COUNT_DATA_LSB 0
#define FRC1_COUNT_DATA_MASK 0x007fffff
//CPU0 Interrupt number reserved, not touch this.
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_FROM_CPU_INUM 2
#define ETS_T0_WDT_INUM 3
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
#define FRC1_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR +0x08)
#define FRC1_CTRL_DATA_MSB 7
#define FRC1_CTRL_DATA_LSB 0
#define FRC1_CTRL_DATA_MASK 0x000000ff
//CPU0 Intrrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
//clear timer1's interrupt when write this address
#define FRC1_INT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x0c)
#define FRC1_INT_CLR_MSB 0
#define FRC1_INT_CLR_LSB 0
#define FRC1_INT_CLR_MASK 0x00000001
//only used for simulation
#define FRC1_TEST_ADDRESS (PERIPHS_TIMER_BASEDDR +0x10)
#define FRC1_TEST_MODE_MSB 0
#define FRC1_TEST_MODE_LSB 0
#define FRC1_TEST_MODE_MASK 0x00000001
//load initial_value to timer2
#define FRC2_LOAD_ADDRESS (PERIPHS_TIMER_BASEDDR +0x20)
#define FRC2_LOAD_DATA_MSB 31
#define FRC2_LOAD_DATA_LSB 0
#define FRC2_LOAD_DATA_MASK 0xffffffff
//timer2's counter value(count from initial_value to 0)
#define FRC2_COUNT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x24)
#define FRC2_COUNT_DATA_MSB 31
#define FRC2_COUNT_DATA_LSB 0
#define FRC2_COUNT_DATA_MASK 0xffffffff
#define FRC2_CTRL_ADDRESS (PERIPHS_TIMER_BASEDDR +0x28)
#define FRC2_CTRL_DATA_MSB 7
#define FRC2_CTRL_DATA_LSB 0
#define FRC2_CTRL_DATA_MASK 0x000000ff
//clear interrupt when write this address
#define FRC2_INT_ADDRESS (PERIPHS_TIMER_BASEDDR +0x2c)
#define FRC2_INT_CLR_MSB 0
#define FRC2_INT_CLR_LSB 0
#define FRC2_INT_CLR_MASK 0x00000001
//set Alarm_value for timer2 to generate interrupt
#define FRC2_ALARM_ADDRESS (PERIPHS_TIMER_BASEDDR +0x30)
#define FRC2_ALARM_DATA_MSB 31
#define FRC2_ALARM_DATA_LSB 0
#define FRC2_ALARM_DATA_MASK 0xffffffff
// }}
#define SPI_ENCRYPT_CNTL (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x20)
#define SPI_ENCRYPT_CNTL_ENA BIT(0)
#define SPI_ENCRYPT_ADDR (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x24)
#define SPI_ENCRYPT_CHECKDONE (PERIPHS_SPI_ENCRYPT_BASEADDR + 0x28)
#define SPI_ENCRYPT_CHECKDONE_STATUS BIT(0)
#endif /* _ESP32_SOC_H_ */

88
components/esp32/include/soc/timers_reg.h
View File

@@ -16,7 +16,7 @@
#include "soc.h"
#define T0CONFIG (DR_REG_TIMERS_BASE + 0x0000)
#define T0CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0000)
#define TIMERS_T0_EN (BIT(31))
#define TIMERS_T0_EN_S 31
#define TIMERS_T0_INCREASE (BIT(30))
@@ -32,39 +32,39 @@
#define TIMERS_T0_ALARM_EN (BIT(10))
#define TIMERS_T0_ALARM_EN_S 10
#define T0LO (DR_REG_TIMERS_BASE + 0x0004)
#define T0LO(i) (DR_REG_TIMERS_BASE(i) + 0x0004)
#define TIMERS_T0_LO 0xFFFFFFFF
#define TIMERS_T0_LO_S 0
#define T0HI (DR_REG_TIMERS_BASE + 0x0008)
#define T0HI(i) (DR_REG_TIMERS_BASE(i) + 0x0008)
#define TIMERS_T0_HI 0xFFFFFFFF
#define TIMERS_T0_HI_S 0
#define T0UPDATE (DR_REG_TIMERS_BASE + 0x000c)
#define T0UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x000c)
#define TIMERS_T0_UPDATE 0xFFFFFFFF
#define TIMERS_T0_UPDATE_S 0
#define T0ALARMLO (DR_REG_TIMERS_BASE + 0x0010)
#define T0ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0010)
#define TIMERS_T0_ALARM_LO 0xFFFFFFFF
#define TIMERS_T0_ALARM_LO_S 0
#define T0ALARMHI (DR_REG_TIMERS_BASE + 0x0014)
#define T0ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0014)
#define TIMERS_T0_ALARM_HI 0xFFFFFFFF
#define TIMERS_T0_ALARM_HI_S 0
#define T0LOADLO (DR_REG_TIMERS_BASE + 0x0018)
#define T0LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x0018)
#define TIMERS_T0_LOAD_LO 0xFFFFFFFF
#define TIMERS_T0_LOAD_LO_S 0
#define T0LOADHI (DR_REG_TIMERS_BASE + 0x001c)
#define T0LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x001c)
#define TIMERS_T0_LOAD_HI 0xFFFFFFFF
#define TIMERS_T0_LOAD_HI_S 0
#define T0LOAD (DR_REG_TIMERS_BASE + 0x0020)
#define T0LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0020)
#define TIMERS_T0_LOAD 0xFFFFFFFF
#define TIMERS_T0_LOAD_S 0
#define T1CONFIG (DR_REG_TIMERS_BASE + 0x0024)
#define T1CONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0024)
#define TIMERS_T1_EN (BIT(31))
#define TIMERS_T1_EN_S 31
#define TIMERS_T1_INCREASE (BIT(30))
@@ -80,39 +80,39 @@
#define TIMERS_T1_ALARM_EN (BIT(10))
#define TIMERS_T1_ALARM_EN_S 10
#define T1LO (DR_REG_TIMERS_BASE + 0x0028)
#define T1LO(i) (DR_REG_TIMERS_BASE(i) + 0x0028)
#define TIMERS_T1_LO 0xFFFFFFFF
#define TIMERS_T1_LO_S 0
#define T1HI (DR_REG_TIMERS_BASE + 0x002c)
#define T1HI(i) (DR_REG_TIMERS_BASE(i) + 0x002c)
#define TIMERS_T1_HI 0xFFFFFFFF
#define TIMERS_T1_HI_S 0
#define T1UPDATE (DR_REG_TIMERS_BASE + 0x0030)
#define T1UPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0030)
#define TIMERS_T1_UPDATE 0xFFFFFFFF
#define TIMERS_T1_UPDATE_S 0
#define T1ALARMLO (DR_REG_TIMERS_BASE + 0x0034)
#define T1ALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0034)
#define TIMERS_T1_ALARM_LO 0xFFFFFFFF
#define TIMERS_T1_ALARM_LO_S 0
#define T1ALARMHI (DR_REG_TIMERS_BASE + 0x0038)
#define T1ALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0038)
#define TIMERS_T1_ALARM_HI 0xFFFFFFFF
#define TIMERS_T1_ALARM_HI_S 0
#define T1LOADLO (DR_REG_TIMERS_BASE + 0x003c)
#define T1LOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x003c)
#define TIMERS_T1_LOAD_LO 0xFFFFFFFF
#define TIMERS_T1_LOAD_LO_S 0
#define T1LOADHI (DR_REG_TIMERS_BASE + 0x0040)
#define T1LOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0040)
#define TIMERS_T1_LOAD_HI 0xFFFFFFFF
#define TIMERS_T1_LOAD_HI_S 0
#define T1LOAD (DR_REG_TIMERS_BASE + 0x0044)
#define T1LOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0044)
#define TIMERS_T1_LOAD 0xFFFFFFFF
#define TIMERS_T1_LOAD_S 0
#define WDTCONFIG0 (DR_REG_TIMERS_BASE + 0x0048)
#define WDTCONFIG0(i) (DR_REG_TIMERS_BASE(i) + 0x0048)
#define TIMERS_WDT_EN (BIT(31))
#define TIMERS_WDT_EN_S 31
#define TIMERS_WDT_STG0 0x00000003
@@ -134,35 +134,35 @@
#define TIMERS_WDT_FLASHBOOT_MOD_EN (BIT(14))
#define TIMERS_WDT_FLASHBOOT_MOD_EN_S 14
#define WDTCONFIG1 (DR_REG_TIMERS_BASE + 0x004c)
#define WDTCONFIG1(i) (DR_REG_TIMERS_BASE(i) + 0x004c)
#define TIMERS_WDT_CLK_PRESCALE 0x0000FFFF
#define TIMERS_WDT_CLK_PRESCALE_S 16
#define WDTCONFIG2 (DR_REG_TIMERS_BASE + 0x0050)
#define WDTCONFIG2(i) (DR_REG_TIMERS_BASE(i) + 0x0050)
#define TIMERS_WDT_STG0_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG0_HOLD_S 0
#define WDTCONFIG3 (DR_REG_TIMERS_BASE + 0x0054)
#define WDTCONFIG3(i) (DR_REG_TIMERS_BASE(i) + 0x0054)
#define TIMERS_WDT_STG1_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG1_HOLD_S 0
#define WDTCONFIG4 (DR_REG_TIMERS_BASE + 0x0058)
#define WDTCONFIG4(i) (DR_REG_TIMERS_BASE(i) + 0x0058)
#define TIMERS_WDT_STG2_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG2_HOLD_S 0
#define WDTCONFIG5 (DR_REG_TIMERS_BASE + 0x005c)
#define WDTCONFIG5(i) (DR_REG_TIMERS_BASE(i) + 0x005c)
#define TIMERS_WDT_STG3_HOLD 0xFFFFFFFF
#define TIMERS_WDT_STG3_HOLD_S 0
#define WDTFEED (DR_REG_TIMERS_BASE + 0x0060)
#define WDTFEED(i) (DR_REG_TIMERS_BASE(i) + 0x0060)
#define TIMERS_WDT_FEED 0xFFFFFFFF
#define TIMERS_WDT_FEED_S 0
#define WDTWPROTECT (DR_REG_TIMERS_BASE + 0x0064)
#define WDTWPROTECT(i) (DR_REG_TIMERS_BASE(i) + 0x0064)
#define TIMERS_WDT_WKEY 0xFFFFFFFF
#define TIMERS_WDT_WKEY_S 0
#define RTCCALICFG (DR_REG_TIMERS_BASE + 0x0068)
#define RTCCALICFG(i) (DR_REG_TIMERS_BASE(i) + 0x0068)
#define TIMERS_RTC_CALI_START (BIT(31))
#define TIMERS_RTC_CALI_START_S 31
#define TIMERS_RTC_CALI_MAX 0x00007FFF
@@ -174,11 +174,11 @@
#define TIMERS_RTC_CALI_START_CYCLING (BIT(12))
#define TIMERS_RTC_CALI_START_CYCLING_S 12
#define RTCCALICFG1 (DR_REG_TIMERS_BASE + 0x006c)
#define RTCCALICFG1(i) (DR_REG_TIMERS_BASE(i) + 0x006c)
#define TIMERS_RTC_CALI_VALUE 0x01FFFFFF
#define TIMERS_RTC_CALI_VALUE_S 7
#define LACTCONFIG (DR_REG_TIMERS_BASE + 0x0070)
#define LACTCONFIG(i) (DR_REG_TIMERS_BASE(i) + 0x0070)
#define TIMERS_LACT_EN (BIT(31))
#define TIMERS_LACT_EN_S 31
#define TIMERS_LACT_INCREASE (BIT(30))
@@ -200,43 +200,43 @@
#define TIMERS_LACT_RTC_ONLY (BIT(7))
#define TIMERS_LACT_RTC_ONLY_S 7
#define LACTRTC (DR_REG_TIMERS_BASE + 0x0074)
#define LACTRTC(i) (DR_REG_TIMERS_BASE(i) + 0x0074)
#define TIMERS_LACT_RTC_STEP_LEN 0x03FFFFFF
#define TIMERS_LACT_RTC_STEP_LEN_S 6
#define LACTLO (DR_REG_TIMERS_BASE + 0x0078)
#define LACTLO(i) (DR_REG_TIMERS_BASE(i) + 0x0078)
#define TIMERS_LACT_LO 0xFFFFFFFF
#define TIMERS_LACT_LO_S 0
#define LACTHI (DR_REG_TIMERS_BASE + 0x007c)
#define LACTHI(i) (DR_REG_TIMERS_BASE(i) + 0x007c)
#define TIMERS_LACT_HI 0xFFFFFFFF
#define TIMERS_LACT_HI_S 0
#define LACTUPDATE (DR_REG_TIMERS_BASE + 0x0080)
#define LACTUPDATE(i) (DR_REG_TIMERS_BASE(i) + 0x0080)
#define TIMERS_LACT_UPDATE 0xFFFFFFFF
#define TIMERS_LACT_UPDATE_S 0
#define LACTALARMLO (DR_REG_TIMERS_BASE + 0x0084)
#define LACTALARMLO(i) (DR_REG_TIMERS_BASE(i) + 0x0084)
#define TIMERS_LACT_ALARM_LO 0xFFFFFFFF
#define TIMERS_LACT_ALARM_LO_S 0
#define LACTALARMHI (DR_REG_TIMERS_BASE + 0x0088)
#define LACTALARMHI(i) (DR_REG_TIMERS_BASE(i) + 0x0088)
#define TIMERS_LACT_ALARM_HI 0xFFFFFFFF
#define TIMERS_LACT_ALARM_HI_S 0
#define LACTLOADLO (DR_REG_TIMERS_BASE + 0x008c)
#define LACTLOADLO(i) (DR_REG_TIMERS_BASE(i) + 0x008c)
#define TIMERS_LACT_LOAD_LO 0xFFFFFFFF
#define TIMERS_LACT_LOAD_LO_S 0
#define LACTLOADHI (DR_REG_TIMERS_BASE + 0x0090)
#define LACTLOADHI(i) (DR_REG_TIMERS_BASE(i) + 0x0090)
#define TIMERS_LACT_LOAD_HI 0xFFFFFFFF
#define TIMERS_LACT_LOAD_HI_S 0
#define LACTLOAD (DR_REG_TIMERS_BASE + 0x0094)
#define LACTLOAD(i) (DR_REG_TIMERS_BASE(i) + 0x0094)
#define TIMERS_LACT_LOAD 0xFFFFFFFF
#define TIMERS_LACT_LOAD_S 0
#define INT_ENA_TIMERS (DR_REG_TIMERS_BASE + 0x0098)
#define INT_ENA_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x0098)
#define TIMERS_LACT_INT_ENA (BIT(3))
#define TIMERS_LACT_INT_ENA_S 3
#define TIMERS_WDT_INT_ENA (BIT(2))
@@ -246,7 +246,7 @@
#define TIMERS_T0_INT_ENA (BIT(0))
#define TIMERS_T0_INT_ENA_S 0
#define INT_RAW_TIMERS (DR_REG_TIMERS_BASE + 0x009c)
#define INT_RAW_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x009c)
#define TIMERS_LACT_INT_RAW (BIT(3))
#define TIMERS_LACT_INT_RAW_S 3
#define TIMERS_WDT_INT_RAW (BIT(2))
@@ -256,7 +256,7 @@
#define TIMERS_T0_INT_RAW (BIT(0))
#define TIMERS_T0_INT_RAW_S 0
#define INT_ST_TIMERS (DR_REG_TIMERS_BASE + 0x00a0)
#define INT_ST_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a0)
#define TIMERS_LACT_INT_ST (BIT(3))
#define TIMERS_LACT_INT_ST_S 3
#define TIMERS_WDT_INT_ST (BIT(2))
@@ -266,7 +266,7 @@
#define TIMERS_T0_INT_ST (BIT(0))
#define TIMERS_T0_INT_ST_S 0
#define INT_CLR_TIMERS (DR_REG_TIMERS_BASE + 0x00a4)
#define INT_CLR_TIMERS(i) (DR_REG_TIMERS_BASE(i) + 0x00a4)
#define TIMERS_LACT_INT_CLR (BIT(3))
#define TIMERS_LACT_INT_CLR_S 3
#define TIMERS_WDT_INT_CLR (BIT(2))
@@ -276,12 +276,12 @@
#define TIMERS_T0_INT_CLR (BIT(0))
#define TIMERS_T0_INT_CLR_S 0
#define NTIMERS_DATE (DR_REG_TIMERS_BASE + 0x00f8)
#define NTIMERS_DATE(i) (DR_REG_TIMERS_BASE(i) + 0x00f8)
#define TIMERS_NTIMERS_DATE 0x0FFFFFFF
#define TIMERS_NTIMERS_DATE_S 0
#define TIMERS_NTIMERS_DATE_VERSION 0x1604290
#define REGCLK (DR_REG_TIMERS_BASE + 0x00fc)
#define REGCLK(i) (DR_REG_TIMERS_BASE(i) + 0x00fc)
#define TIMERS_CLK_EN (BIT(31))
#define TIMERS_CLK_EN_S 31