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soc: move peripheral base address into reg_base.h

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morris
2022-01-05 16:14:03 +08:00
parent 8cdcb4e291
commit 24acdf23ee
18 changed files with 394 additions and 452 deletions
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18
components/soc/esp32c3/include/soc/periph_defs.h
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once

48
components/soc/esp32c3/include/soc/reg_base.h Normal file
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@@ -0,0 +1,48 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_EXTMEM_BASE 0x600c4000
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_AES_BASE 0x6003a000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_RSA_BASE 0x6003c000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
#define DR_REG_GDMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000
#define DR_REG_GPIO_BASE 0x60004000
#define DR_REG_FE2_BASE 0x60005000
#define DR_REG_FE_BASE 0x60006000
#define DR_REG_RTCCNTL_BASE 0x60008000
#define DR_REG_IO_MUX_BASE 0x60009000
#define DR_REG_RTC_I2C_BASE 0x6000e000
#define DR_REG_UART1_BASE 0x60010000
#define DR_REG_I2C_EXT_BASE 0x60013000
#define DR_REG_UHCI0_BASE 0x60014000
#define DR_REG_RMT_BASE 0x60016000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_EFUSE_BASE 0x60008800
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_I2S0_BASE 0x6002D000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000
#define DR_REG_AES_XTS_BASE 0x600CC000

56
components/soc/esp32c3/include/soc/soc.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,54 +9,12 @@
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#include "esp_bit_defs.h"
#endif
#define PRO_CPU_NUM (0)
#include "esp_bit_defs.h"
#include "reg_base.h"
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_EXTMEM_BASE 0x600c4000
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_AES_BASE 0x6003a000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_RSA_BASE 0x6003c000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
#define DR_REG_GDMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000
#define DR_REG_GPIO_BASE 0x60004000
#define DR_REG_FE2_BASE 0x60005000
#define DR_REG_FE_BASE 0x60006000
#define DR_REG_RTCCNTL_BASE 0x60008000
#define DR_REG_IO_MUX_BASE 0x60009000
#define DR_REG_RTC_I2C_BASE 0x6000e000
#define DR_REG_UART1_BASE 0x60010000
#define DR_REG_I2C_EXT_BASE 0x60013000
#define DR_REG_UHCI0_BASE 0x60014000
#define DR_REG_RMT_BASE 0x60016000
#define DR_REG_LEDC_BASE 0x60019000
#define DR_REG_EFUSE_BASE 0x60008800
#define DR_REG_NRX_BASE 0x6001CC00
#define DR_REG_BB_BASE 0x6001D000
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
#define DR_REG_TIMERGROUP1_BASE 0x60020000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_SPI2_BASE 0x60024000
#define DR_REG_SYSCON_BASE 0x60026000
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_I2S0_BASE 0x6002D000
#define DR_REG_APB_SARADC_BASE 0x60040000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000
#define DR_REG_AES_XTS_BASE 0x600CC000
#define PRO_CPU_NUM (0)
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000)
@@ -71,12 +29,6 @@
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
#define BIT(nr) (1UL << (nr))
#else
#define BIT(nr) (1 << (nr))
#endif
#ifndef __ASSEMBLER__
//write value to register