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soc: move peripheral base address into reg_base.h

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morris
2022-01-05 16:14:03 +08:00
parent 8cdcb4e291
commit 24acdf23ee
18 changed files with 394 additions and 452 deletions
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87
components/soc/esp32s2/include/soc/soc.h
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@@ -1,88 +1,23 @@
// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#include "esp_bit_defs.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
#define DR_REG_SYSTEM_BASE 0x3f4c0000
#define DR_REG_SENSITIVE_BASE 0x3f4c1000
#define DR_REG_INTERRUPT_BASE 0x3f4c2000
#define DR_REG_DMA_COPY_BASE 0x3f4c3000
#define DR_REG_EXTMEM_BASE 0x61800000
#define DR_REG_MMU_TABLE 0x61801000
#define DR_REG_ITAG_TABLE 0x61802000
#define DR_REG_DTAG_TABLE 0x61803000
#define DR_REG_AES_BASE 0x6003a000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_RSA_BASE 0x6003c000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
#define DR_REG_INTRUSION_BASE 0x3f4d0000
#define DR_REG_DPORT_END 0x3f4d3FFC
#define DR_REG_UART_BASE 0x3f400000
#define DR_REG_SPI1_BASE 0x3f402000
#define DR_REG_SPI0_BASE 0x3f403000
#define DR_REG_GPIO_BASE 0x3f404000
#define DR_REG_GPIO_SD_BASE 0x3f404f00
#define DR_REG_FE2_BASE 0x3f405000
#define DR_REG_FE_BASE 0x3f406000
#define DR_REG_FRC_TIMER_BASE 0x3f407000
#define DR_REG_RTCCNTL_BASE 0x3f408000
#define DR_REG_RTCIO_BASE 0x3f408400
#define DR_REG_SENS_BASE 0x3f408800
#define DR_REG_RTC_I2C_BASE 0x3f408C00
#define DR_REG_IO_MUX_BASE 0x3f409000
#define DR_REG_HINF_BASE 0x3f40B000
#define DR_REG_I2S_BASE 0x3f40F000
#define DR_REG_UART1_BASE 0x3f410000
#define DR_REG_I2C_EXT_BASE 0x3f413000
#define DR_REG_UHCI0_BASE 0x3f414000
#define DR_REG_SLCHOST_BASE 0x3f415000
#define DR_REG_RMT_BASE 0x3f416000
#define DR_REG_PCNT_BASE 0x3f417000
#define DR_REG_SLC_BASE 0x3f418000
#define DR_REG_LEDC_BASE 0x3f419000
#define DR_REG_CP_BASE 0x3f4c3000
#define DR_REG_EFUSE_BASE 0x3f41A000
#define DR_REG_NRX_BASE 0x3f41CC00
#define DR_REG_BB_BASE 0x3f41D000
#define DR_REG_TIMERGROUP0_BASE 0x3f41F000
#define DR_REG_TIMERGROUP1_BASE 0x3f420000
#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000
#define DR_REG_SYSTIMER_BASE 0x3f423000
#define DR_REG_SPI2_BASE 0x3f424000
#define DR_REG_SPI3_BASE 0x3f425000
#define DR_REG_SYSCON_BASE 0x3f426000
#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x3f427000
#define DR_REG_SPI4_BASE 0x3f437000
#define DR_REG_USB_WRAP_BASE 0x3f439000
#define DR_REG_APB_SARADC_BASE 0x3f440000
#define DR_REG_USB_BASE 0x60080000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
@@ -100,12 +35,6 @@
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
#define BIT(nr) (1UL << (nr))
#else
#define BIT(nr) (1 << (nr))
#endif
#ifndef __ASSEMBLER__
#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)