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feat(esp32c5mp): add system related components

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This commit is contained in:
laokaiyao
2024-03-13 16:58:13 +08:00
parent cd1b0dafa7
commit 24d6dcb829
27 changed files with 1067 additions and 56 deletions
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25
components/esp_system/port/soc/esp32c5/system_internal.c
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@@ -13,16 +13,21 @@
#include "esp_rom_sys.h"
#include "riscv/rv_utils.h"
#include "esp_rom_uart.h"
#include "soc/soc_caps.h"
#include "soc/gpio_reg.h"
#include "esp_cpu.h"
#include "soc/rtc.h"
#include "esp_private/rtc_clk.h"
#include "soc/rtc_periph.h"
#include "soc/uart_reg.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
#include "hal/clk_tree_ll.h"
#endif
#include "hal/wdt_hal.h"
#if SOC_MODEM_CLOCK_SUPPORTED
#include "hal/modem_syscon_ll.h"
#include "hal/modem_lpcon_ll.h"
#endif
#include "esp_private/cache_err_int.h"
#include "esp32c5/rom/cache.h"
@@ -35,32 +40,48 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
esp_rom_output_tx_wait_idle(0);
esp_rom_output_tx_wait_idle(1);
// TODO: IDF-8845
#if SOC_MODEM_CLOCK_SUPPORTED
modem_syscon_ll_reset_all(&MODEM_SYSCON);
modem_lpcon_ll_reset_all(&MODEM_LPCON);
#endif
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
// Set SPI Flash Freq to 40M
clk_ll_mspi_fast_set_src(MSPI_CLK_SRC_XTAL);
clk_ll_mspi_fast_set_divider(1);
// Set Peripheral clk rst
SET_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
#endif
// Set Peripheral clk rst
SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
#endif
// Clear Peripheral clk rst
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
// CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
#endif
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
}
@@ -98,7 +119,11 @@ void IRAM_ATTR esp_restart_noos(void)
wdt_hal_write_protect_enable(&wdt1_context);
// Disable cache
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
Cache_Disable_ICache();
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
Cache_Disable_Cache();
#endif
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
// Moved to module internal