esp_hw_support/sleep: fix current leakage when hold digital io during deep sleep

components/soc/esp32/gpio_periph.c

@@ -13,6 +13,7 @@
 // limitations under the License.
 
 #include "soc/gpio_periph.h"
+#include "esp_attr.h"
 
 const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
     IO_MUX_GPIO0_REG,
@@ -99,3 +100,46 @@ const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
     0,
     0,
 };
+
+DRAM_ATTR const uint8_t GPIO_PIN_MUX_REG_OFFSET[] = {
+    0x44,
+    0x88,
+    0x40,
+    0x84,
+    0x48,
+    0x6c,
+    0x60,
+    0x64,
+    0x68,
+    0x54,
+    0x58,
+    0x5c,
+    0x34,
+    0x38,
+    0x30,
+    0x3c,
+    0x4c,
+    0x50,
+    0x70,
+    0x74,
+    0x78,
+    0x7c,
+    0x80,
+    0x8c,
+    0xFF, // 24
+    0x24,
+    0x28,
+    0x2c,
+    0xFF, // 28
+    0xFF, // 29
+    0xFF, // 30
+    0xFF, // 31
+    0x1c,
+    0x20,
+    0x14,
+    0x18,
+    0x04,
+    0x08,
+    0x0c,
+    0x10,
+};

components/soc/esp32/include/soc/soc_caps.h

@@ -121,6 +121,9 @@
 // GPIO >= 34 are input only
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))
 
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM: 1, 3, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 21, 22, 23)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0xEF0FEAULL
+
 // Support to configure slept status
 #define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)