alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-08 04:02:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(efuse): Update efuses for C5 and C61

Browse Source
This commit is contained in:
Konstantin Kondrashov
2024-03-13 22:51:44 +02:00
parent 22b5f69f7b
commit 25bc10e143
35 changed files with 4482 additions and 3285 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
components/hal/esp32c5/efuse_hal.c
View File

@@ -38,75 +38,59 @@ IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
void efuse_hal_set_timing(uint32_t apb_freq_hz)
{
(void) apb_freq_hz;
// TODO: [ESP32C5] IDF-8674
abort();
// efuse_ll_set_dac_num(0xFF);
// efuse_ll_set_dac_clk_div(0x28);
// efuse_ll_set_pwr_on_num(0x3000);
// efuse_ll_set_pwr_off_num(0x190);
}
void efuse_hal_read(void)
{
// TODO: [ESP32C5] IDF-8674
abort();
// efuse_hal_set_timing(0);
efuse_hal_set_timing(0);
// efuse_ll_set_conf_read_op_code();
// efuse_ll_set_read_cmd();
efuse_ll_set_conf_read_op_code();
efuse_ll_set_read_cmd();
// while (efuse_ll_get_read_cmd() != 0) { }
// /*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
// while (efuse_ll_get_read_cmd() != 0) { }
while (efuse_ll_get_read_cmd() != 0) { }
/*Due to a hardware error, we have to read READ_CMD again to make sure the efuse clock is normal*/
while (efuse_ll_get_read_cmd() != 0) { }
}
void efuse_hal_clear_program_registers(void)
{
// TODO: [ESP32C5] IDF-8674
abort();
// ets_efuse_clear_program_registers();
ets_efuse_clear_program_registers();
}
void efuse_hal_program(uint32_t block)
{
// TODO: [ESP32C5] IDF-8674
abort();
// efuse_hal_set_timing(0);
efuse_hal_set_timing(0);
// efuse_ll_set_conf_write_op_code();
// efuse_ll_set_pgm_cmd(block);
efuse_ll_set_conf_write_op_code();
efuse_ll_set_pgm_cmd(block);
// while (efuse_ll_get_pgm_cmd() != 0) { }
while (efuse_ll_get_pgm_cmd() != 0) { }
// efuse_hal_clear_program_registers();
// efuse_hal_read();
efuse_hal_clear_program_registers();
efuse_hal_read();
}
void efuse_hal_rs_calculate(const void *data, void *rs_values)
{
// TODO: [ESP32C5] IDF-8674
abort();
// ets_efuse_rs_calculate(data, rs_values);
ets_efuse_rs_calculate(data, rs_values);
}
/******************* eFuse control functions *************************/
bool efuse_hal_is_coding_error_in_block(unsigned block)
{
// TODO: [ESP32C5] IDF-8674
abort();
// if (block == 0) {
// for (unsigned i = 0; i < 5; i++) {
// if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
// return true;
// }
// }
// } else if (block <= 10) {
// // EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
// // EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
// block--;
// uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
// return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
// }
if (block == 0) {
for (unsigned i = 0; i < 5; i++) {
if (REG_READ(EFUSE_RD_REPEAT_DATA_ERR0_REG + i * 4)) {
return true;
}
}
} else if (block <= 10) {
// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
block--;
uint32_t error_reg = REG_READ(EFUSE_RD_RS_DATA_ERR0_REG + (block / 8) * 4);
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
}
return false;
}