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https://github.com/espressif/esp-idf.git
synced 2025-09-19 08:03:59 +00:00
fix(spi_slave): correct param check for trans APIs
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@@ -401,10 +401,16 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi
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SPI_CHECK(spihost[host], "host not slave", ESP_ERR_INVALID_ARG);
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SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->tx_buffer == NULL || esp_ptr_dma_capable(trans_desc->tx_buffer),
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"txdata not in DMA-capable memory", ESP_ERR_INVALID_ARG);
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// We don't check length WORD alignment for rx when using DMA, seems break DMA requirement,
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// however peripheral can also stop DMA from over writing memory even if it not aligned (except esp32).
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// ATTENTION!: On esp32, peripheral can NOT stop DMA, if length not WORD aligned,
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// remain bytes in last word domain will overwritten by DMA HW, which may cause unexpected issues!
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// But driver already used for long time, to avoid breaking changes, we still don't add alignment limit.
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SPI_CHECK(spihost[host]->dma_enabled == 0 || trans_desc->rx_buffer == NULL ||
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(esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) &&
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(trans_desc->length % 4 == 0)),
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"rxdata not in DMA-capable memory or not WORD aligned", ESP_ERR_INVALID_ARG);
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(trans_desc->length % 8 == 0)),
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"rxdata not in DMA-capable memory or not BYTE aligned", ESP_ERR_INVALID_ARG);
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SPI_CHECK(trans_desc->length <= spihost[host]->max_transfer_sz * 8, "data transfer > host maximum", ESP_ERR_INVALID_ARG);
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@@ -423,6 +429,7 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_queue_trans(spi_host_device_t host, const spi
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* @note
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* This API is used to reset SPI Slave transaction queue. After calling this function:
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* - The SPI Slave transaction queue will be reset.
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* - The transaction which already mount on hardware will NOT be reset, and can be overwritten by next `trans_queue`
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*
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* Therefore, this API shouldn't be called when the corresponding SPI Master is doing an SPI transaction.
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*
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@@ -460,20 +467,20 @@ esp_err_t SPI_SLAVE_ISR_ATTR spi_slave_queue_trans_isr(spi_host_device_t host, c
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ESP_RETURN_ON_FALSE_ISR(trans_desc->length <= spihost[host]->max_transfer_sz * 8, ESP_ERR_INVALID_ARG, SPI_TAG, "data transfer > host maximum");
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if (spihost[host]->dma_enabled) {
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uint16_t alignment = spihost[host]->internal_mem_align_size;
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uint32_t buffer_byte_len = (trans_desc->length + 7) / 8;
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(void) alignment;
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ESP_RETURN_ON_FALSE_ISR(\
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(trans_desc->tx_buffer && \
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esp_ptr_dma_capable(trans_desc->tx_buffer) && \
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((((uint32_t)trans_desc->tx_buffer) | buffer_byte_len) & (alignment - 1)) == 0), \
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ESP_ERR_INVALID_ARG, SPI_TAG, "txdata addr & len not align to %d bytes or not dma_capable", alignment\
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);
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ESP_RETURN_ON_FALSE_ISR(\
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(trans_desc->rx_buffer && \
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esp_ptr_dma_capable(trans_desc->rx_buffer) && \
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((((uint32_t)trans_desc->rx_buffer) | buffer_byte_len) & (alignment - 1)) == 0), \
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ESP_ERR_INVALID_ARG, SPI_TAG, "rxdata addr & len not align to %d bytes or not dma_capable", alignment\
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);
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#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
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// For those targets length and addr alignment is still required from Cache side
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uint32_t buffer_byte_len = (trans_desc->length + 7) / 8;
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bool tx_aligned = (trans_desc->tx_buffer == NULL) || (esp_ptr_dma_capable(trans_desc->tx_buffer) && ((((uint32_t)trans_desc->tx_buffer | buffer_byte_len) & (alignment - 1)) == 0));
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bool rx_aligned = (trans_desc->rx_buffer == NULL) || (esp_ptr_dma_capable(trans_desc->rx_buffer) && ((((uint32_t)trans_desc->rx_buffer | buffer_byte_len) & (alignment - 1)) == 0));
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#else
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bool tx_aligned = (trans_desc->tx_buffer == NULL) || esp_ptr_dma_capable(trans_desc->tx_buffer);
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bool rx_aligned = (trans_desc->rx_buffer == NULL) || (esp_ptr_dma_capable(trans_desc->rx_buffer) && esp_ptr_word_aligned(trans_desc->rx_buffer) && (trans_desc->length % 8 == 0));
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#endif
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ESP_RETURN_ON_FALSE_ISR(tx_aligned, ESP_ERR_INVALID_ARG, SPI_TAG, "txdata addr & len not align to %d bytes or not dma_capable", alignment);
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ESP_RETURN_ON_FALSE_ISR(rx_aligned, ESP_ERR_INVALID_ARG, SPI_TAG, "rxdata addr & len not align to %d bytes or not dma_capable", alignment);
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}
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spi_slave_trans_priv_t priv_trans = {
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