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fix(freertos): Use INTERRUPT_CURRENT_CORE_INT_THRESH_REG for esp32p4

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This commit is contained in:
KonstantinKondrashov
2023-09-07 15:25:35 +08:00
parent 02b6c1f0ca
commit 25c7a59e31
10 changed files with 37 additions and 16 deletions
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2
components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h
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@@ -638,7 +638,7 @@ static inline void __attribute__((always_inline)) vPortExitCriticalSafe(portMUX_
FORCE_INLINE_ATTR bool xPortCanYield(void)
{
uint32_t threshold = REG_READ(INTERRUPT_CORE0_CPU_INT_THRESH_REG);
uint32_t threshold = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
#if SOC_INT_CLIC_SUPPORTED
threshold = threshold >> (CLIC_CPU_INT_THRESH_S + (8 - NLBITS));

7
components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
View File

@@ -41,6 +41,7 @@
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/system_reg.h"
#include "soc/interrupt_reg.h"
#include "hal/systimer_hal.h"
#include "hal/systimer_ll.h"
#include "riscv/rvruntime-frames.h"
@@ -367,8 +368,8 @@ UBaseType_t xPortSetInterruptMaskFromISR(void)
#if !SOC_INT_CLIC_SUPPORTED
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
prev_int_level = REG_READ(INTERRUPT_CORE0_CPU_INT_THRESH_REG);
REG_WRITE(INTERRUPT_CORE0_CPU_INT_THRESH_REG, RVHAL_EXCM_LEVEL);
prev_int_level = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, RVHAL_EXCM_LEVEL);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
#else
/* When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */
@@ -391,7 +392,7 @@ UBaseType_t xPortSetInterruptMaskFromISR(void)
void vPortClearInterruptMaskFromISR(UBaseType_t prev_int_level)
{
#if !SOC_INT_CLIC_SUPPORTED
REG_WRITE(INTERRUPT_CORE0_CPU_INT_THRESH_REG, prev_int_level);
REG_WRITE(INTERRUPT_CURRENT_CORE_INT_THRESH_REG, prev_int_level);
#else
rv_utils_restore_intlevel(prev_int_level);
#endif /* SOC_INIT_CLIC_SUPPORTED */