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https://github.com/espressif/esp-idf.git
synced 2025-09-24 17:27:21 +00:00
feat(intr): clean up and support interrupts on H21
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -11,6 +11,7 @@
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#include "esp_intr_alloc.h"
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#include "esp_debug_helpers.h"
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#include "soc/periph_defs.h"
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#include "soc/system_intr.h"
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#include "hal/crosscore_int_ll.h"
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#include "freertos/FreeRTOS.h"
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@@ -20,10 +21,6 @@
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#include "esp_gdbstub.h"
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#endif
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#if CONFIG_IDF_TARGET_ESP32H21
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#define ETS_FROM_CPU_INTR0_SOURCE ETS_CPU_INTR_FROM_CPU_0_SOURCE
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#endif
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#define REASON_YIELD BIT(0)
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#define REASON_FREQ_SWITCH BIT(1)
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#define REASON_PRINT_BACKTRACE BIT(2)
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@@ -98,12 +95,12 @@ void esp_crosscore_int_init(void)
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esp_err_t err __attribute__((unused)) = ESP_OK;
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#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
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if (esp_cpu_get_core_id() == 0) {
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err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
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err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
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} else {
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err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
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err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
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}
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#else
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err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
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err = esp_intr_alloc(SYS_CPU_INTR_FROM_CPU_0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
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#endif
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ESP_ERROR_CHECK(err);
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}
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