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Merge branch 'feature/esp32s2_iram_dram_protection' into 'master'

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esp32s2: IRAM/DRAM memory protection

See merge request espressif/esp-idf!8156
This commit is contained in:
Ivan Grokhotkov
2020-04-23 21:52:54 +08:00
parent 3d868ec05d 7491ea677a
commit 275ed32a11
22 changed files with 1699 additions and 91 deletions
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6
components/esp32/cache_err_int.c
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@@ -33,13 +33,13 @@
void esp_cache_err_int_init(void)
{
uint32_t core_id = xPortGetCoreID();
ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
ESP_INTR_DISABLE(ETS_MEMACCESS_ERR_INUM);
// We do not register a handler for the interrupt because it is interrupt
// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
// a call to the panic handler for
// this interrupt.
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_MEMACCESS_ERR_INUM);
// Enable invalid cache access interrupt when the cache is disabled.
// When the interrupt happens, we can not determine the CPU where the
@@ -67,7 +67,7 @@ void esp_cache_err_int_init(void)
DPORT_CACHE_IA_INT_APP_IRAM0 |
DPORT_CACHE_IA_INT_APP_IRAM1);
}
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
ESP_INTR_ENABLE(ETS_MEMACCESS_ERR_INUM);
}
int IRAM_ATTR esp_cache_err_get_cpuid(void)

2
components/esp32/include/esp32/cache_err_int.h
View File

@@ -17,7 +17,7 @@
* @brief initialize cache invalid access interrupt
*
* This function enables cache invalid access interrupt source and connects it
* to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
* to interrupt input number ETS_MEMACCESS_ERR_INUM (see soc/soc.h). It is called
* from the startup code.
*/
void esp_cache_err_int_init(void);