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i2s: update documents for driver-NG

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This commit is contained in:
laokaiyao
2022-04-07 15:32:46 +08:00
parent 0fe3bb8ab7
commit 28b8fc6a7e
117 changed files with 10098 additions and 2657 deletions
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10
components/hal/esp32/include/hal/gpio_ll.h
View File

@@ -570,6 +570,16 @@ static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_
PIN_FUNC_SELECT(pin_name, func);
}
/**
* @brief Control the pin in the IOMUX
*
* @param val Control value
*/
static inline __attribute__((always_inline)) void gpio_ll_iomux_pin_ctrl(uint32_t val)
{
WRITE_PERI_REG(PIN_CTRL, val);
}
/**
* @brief Set peripheral output to an GPIO pad through the IOMUX.
*

51
components/hal/esp32/include/hal/i2s_ll.h
View File

@@ -42,6 +42,9 @@ extern "C" {
#define I2S_LL_EVENT_TX_DSCR_ERR BIT(14)
#define I2S_INTR_MAX (UINT32_MAX)
#define I2S_LL_TX_EVENT_MASK I2S_LL_EVENT_TX_EOF
#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
/* I2S clock configuration structure */
typedef struct {
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a)
@@ -203,6 +206,8 @@ static inline void i2s_ll_tx_reset(i2s_dev_t *hw)
{
hw->conf.tx_reset = 1;
hw->conf.tx_reset = 0;
hw->lc_conf.out_rst = 1;
hw->lc_conf.out_rst = 0;
}
/**
@@ -214,6 +219,8 @@ static inline void i2s_ll_rx_reset(i2s_dev_t *hw)
{
hw->conf.rx_reset = 1;
hw->conf.rx_reset = 0;
hw->lc_conf.in_rst = 1;
hw->lc_conf.in_rst = 0;
}
/**
@@ -248,7 +255,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
//0: disable APLL clock, I2S module will using PLL_D2_CLK(160M) as source clock
//1: Enable APLL clock, I2S module will using APLL as source clock
hw->clkm_conf.clka_en = (src == I2S_CLK_APLL) ? 1 : 0;
hw->clkm_conf.clka_en = (src == I2S_CLK_SRC_APLL) ? 1 : 0;
}
/**
@@ -261,7 +268,7 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
//0: disable APLL clock, I2S module will using PLL_D2_CLK(160M) as source clock
//1: Enable APLL clock, I2S module will using APLL as source clock
hw->clkm_conf.clka_en = (src == I2S_CLK_APLL) ? 1 : 0;
hw->clkm_conf.clka_en = (src == I2S_CLK_SRC_APLL) ? 1 : 0;
}
/**
@@ -444,6 +451,14 @@ static inline uint32_t i2s_ll_get_intr_status(i2s_dev_t *hw)
return hw->int_st.val;
}
/**
* @brief Get channel interrupt status register address
*/
static inline volatile void *i2s_ll_get_interrupt_status_reg(i2s_dev_t *hw)
{
return (volatile void *)(&hw->int_st);
}
/**
* @brief Clear I2S interrupt status
*
@@ -734,17 +749,18 @@ static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enab
* @brief Set I2S tx chan mode
*
* @param hw Peripheral I2S hardware instance address.
* @param slot_sel select slot to send data
* @param slot_mask select slot to send data
* @param is_msb_right the slot sequence is affected by msb_right according to TRM
*/
static inline void i2s_ll_tx_select_slot(i2s_dev_t *hw, i2s_std_slot_sel_t slot_sel)
static inline void i2s_ll_tx_select_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask, bool is_msb_right)
{
switch (slot_sel)
switch (slot_mask)
{
case I2S_STD_SLOT_ONLY_LEFT:
hw->conf_chan.tx_chan_mod = 1;
break;
case I2S_STD_SLOT_ONLY_RIGHT:
hw->conf_chan.tx_chan_mod = 2;
hw->conf_chan.tx_chan_mod = is_msb_right ? 1 : 2;
break;
case I2S_STD_SLOT_ONLY_LEFT:
hw->conf_chan.tx_chan_mod = is_msb_right ? 2 : 1;
break;
case I2S_STD_SLOT_LEFT_RIGHT:
hw->conf_chan.tx_chan_mod = 0;
@@ -758,17 +774,18 @@ static inline void i2s_ll_tx_select_slot(i2s_dev_t *hw, i2s_std_slot_sel_t slot_
* @brief Set I2S rx chan mode
*
* @param hw Peripheral I2S hardware instance address.
* @param slot_sel select slot to receive data
* @param slot_mask select slot to receive data
* @param is_msb_right the slot sequence is affected by msb_right according to TRM
*/
static inline void i2s_ll_rx_select_slot(i2s_dev_t *hw, i2s_std_slot_sel_t slot_sel)
static inline void i2s_ll_rx_select_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask, bool is_msb_right)
{
switch (slot_sel)
switch (slot_mask)
{
case I2S_STD_SLOT_ONLY_LEFT:
hw->conf_chan.rx_chan_mod = 1;
break;
case I2S_STD_SLOT_ONLY_RIGHT:
hw->conf_chan.rx_chan_mod = 2;
hw->conf_chan.rx_chan_mod = is_msb_right ? 1 : 2;
break;
case I2S_STD_SLOT_ONLY_LEFT:
hw->conf_chan.rx_chan_mod = is_msb_right ? 2 : 1;
break;
case I2S_STD_SLOT_LEFT_RIGHT:
hw->conf_chan.rx_chan_mod = 0;
@@ -788,7 +805,6 @@ static inline void i2s_ll_tx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena)
{
int data_bit = hw->sample_rate_conf.tx_bits_mod;
hw->fifo_conf.tx_fifo_mod = data_bit <= I2S_DATA_BIT_WIDTH_16BIT ? mono_ena : 2 + mono_ena;
hw->conf_chan.tx_chan_mod = mono_ena;
}
/**
@@ -801,7 +817,6 @@ static inline void i2s_ll_rx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena)
{
int data_bit = hw->sample_rate_conf.rx_bits_mod;
hw->fifo_conf.rx_fifo_mod = data_bit <= I2S_DATA_BIT_WIDTH_16BIT ? mono_ena : 2 + mono_ena;
hw->conf_chan.rx_chan_mod = mono_ena;
}
/**