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feat(clk): Add basic clock support for esp32h4

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This commit is contained in:
Song Ruo Jing
2025-06-25 17:30:46 +08:00
parent ce92b0ab60
commit 28df79aee8
71 changed files with 697 additions and 937 deletions
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10
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@@ -59,6 +59,10 @@ config SOC_REG_I2C_SUPPORTED
bool
default y
config SOC_CLK_TREE_SUPPORTED
bool
default y
config SOC_WDT_SUPPORTED
bool
default y
@@ -547,6 +551,10 @@ config SOC_PM_RETENTION_MODULE_NUM
int
default 32
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
default y
config SOC_MODEM_CLOCK_IS_INDEPENDENT
bool
default y
@@ -559,7 +567,7 @@ config SOC_CLK_OSC_SLOW_SUPPORTED
bool
default y
config SOC_CLK_RC32K_SUPPORTED
config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
bool
default y

87
components/soc/esp32h4/include/soc/clk_tree_defs.h
View File

@@ -9,37 +9,31 @@
extern "C" {
#endif
// TODO: [ESP32H4] IDF-12285 inherit from verify code, need check
/*
************************* ESP32H4 Root Clock Source ****************************
* 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
* 1) Internal 20MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
*
* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
* This RC oscillator generates a ~20MHz clock signal output as the RC_FAST_CLK.
*
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
*
* 2) External 32MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
* 3) Internal 600kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* This RC oscillator generates a ~600kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
*
* 4) Internal 32kHz RC Oscillator: RC32K
*
* The exact frequency of this clock can be computed in runtime through calibration.
*
* 5) External 32kHz Crystal Clock (optional): XTAL32K
* 4) External 32kHz Crystal Clock (optional): XTAL32K
*
* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
* pins.
*
* XTAL32K_CLK can also be calibrated to get its exact frequency.
*
* 6) External Slow Clock (optional): OSC_SLOW
* 5) External Slow Clock (optional): OSC_SLOW
*
* A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
* A slow clock signal generated by an external circuit can be connected to GPIO5 to be the clock source for the
* RTC_SLOW_CLK.
*
* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
@@ -48,10 +42,9 @@ extern "C" {
/* The pin number to connect the external slow clock (OSC_SLOW_CLK), XTAL_32K_P */
#define SOC_EXT_OSC_SLOW_GPIO_NUM 5
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 20 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 20000000 /*!< Approximate RC_FAST_CLK frequency in Hz */
#define SOC_CLK_RC_SLOW_FREQ_APPROX 600000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
@@ -63,12 +56,11 @@ extern "C" {
* @brief Root clock
*/
typedef enum {
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 20MHz RC oscillator */
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 600kHz RC oscillator */
SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin5 */
} soc_root_clk_t;
/**
@@ -76,6 +68,7 @@ typedef enum {
*/
typedef enum {
SOC_ROOT_CIRCUIT_CLK_BBPLL, /*!< BBPLL_CLK is the output of the PLL generator circuit */
SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
} soc_root_clk_circuit_t;
/**
@@ -84,8 +77,9 @@ typedef enum {
*/
typedef enum {
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_XTAL_X2 = 2, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
SOC_CPU_CLK_SRC_PLL = 3, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
@@ -94,11 +88,12 @@ typedef enum {
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4 = 0, /*!< Select RC_SLOW_D4_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_DEFAULT = SOC_RTC_SLOW_CLK_SRC_RC_SLOW_D4, /*!< RC_SLOW_D4_CLK is the default clock source for RTC_SLOW_CLK */
} soc_rtc_slow_clk_src_t;
/**
@@ -134,19 +129,18 @@ typedef enum {
*/
typedef enum {
// For CPU domain
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or XTAL_X2 by configuring soc_cpu_clk_src_t */
// For RTC domain
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW_D4, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, BLE
SOC_MOD_CLK_XTAL_X2_F32M, /*!< XTAL_X2_F32M_CLK is derived from XTAL_X2 (clock gating + fixed divider of 2), it has a fixed frequency of 32MHz */
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
SOC_MOD_CLK_PLL_F64M, /*!< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 32MHz crystal */
// For LP peripherals
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 32MHz crystal, passing a div of 2 to the LP peripherals */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
@@ -217,15 +211,6 @@ typedef enum {
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< UART source clock default choice is PLL_F48M */
} soc_periph_uart_clk_src_legacy_t;
/**
* @brief Type of LP_UART clock source
*/
typedef enum {
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
} soc_periph_lp_uart_clk_src_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**
@@ -271,10 +256,34 @@ typedef enum {
typedef enum {
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
FLASH_CLK_SRC_REF_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
*/
typedef enum {
CLK_CAL_RC_SLOW = 0, /*!< Select to calibrate RC_SLOW_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
CLK_CAL_32K_OSC_SLOW, /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
CLK_CAL_RC_FAST, /*!< Select to calibrate RC_FAST_CLK */
CLK_CAL_CPU, /*!< Select to calibrate CPU_CLK */
CLK_CAL_AHB, /*!< Select to calibrate AHB_CLK */
CLK_CAL_APB, /*!< Select to calibrate APB_CLK */
CLK_CAL_SEC, /*!< Select to calibrate SEC_CLK */
CLK_CAL_MSPI, /*!< Select to calibrate MSPI_CLK */
CLK_CAL_IOMUX, /*!< Select to calibrate IOMUX_CLK */
CLK_CAL_PARLIO_RX, /*!< Select to calibrate PARLIO_RX_CLK */
CLK_CAL_PARLIO_TX, /*!< Select to calibrate PARLIO_TX_CLK */
CLK_CAL_GPSPI3_MST, /*!< Select to calibrate GPSPI3_MST_CLK */
CLK_CAL_GPSPI2_MST, /*!< Select to calibrate GPSPI2_MST_CLK */
CLK_CAL_EXT_IO, /*!< Select to calibrate an external clock from an IO */
} soc_clk_calibration_clk_src_t;
#ifdef __cplusplus
}
#endif

2
components/soc/esp32h4/include/soc/gpio_sig_map.h
View File

@@ -6,7 +6,7 @@
#pragma once
#define TIMER_IN_IDX 0 // TODO: [ESP32H4] IDF-12499 need check
#define TIMER_IN_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2

4
components/soc/esp32h4/include/soc/regi2c_dcdc.h
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@@ -15,6 +15,10 @@
#define I2C_DCDC 0x6D
#define I2C_DCDC_HOSTID 0
#define I2C_DCDC_XPD_TRX 1
#define I2C_DCDC_XPD_TRX_MSB 7
#define I2C_DCDC_XPD_TRX_LSB 7
#define I2C_DCDC_CCM_DREG0 7
#define I2C_DCDC_CCM_DREG0_MSB 4
#define I2C_DCDC_CCM_DREG0_LSB 0

6
components/soc/esp32h4/include/soc/soc.h
View File

@@ -124,11 +124,9 @@
//}}
//Periheral Clock {{
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define APB_CLK_FREQ ( 40*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define APB_CLK_FREQ ( 32*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 32*1000000 )
#define REF_CLK_FREQ ( 1000000 )
#define XTAL_CLK_FREQ (40*1000000)
//}}
/* Overall memory map */

8
components/soc/esp32h4/include/soc/soc_caps.h
View File

@@ -76,7 +76,7 @@
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32H4] IDF-12449
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32H4] IDF-12445 IDF-12451
#define SOC_REG_I2C_SUPPORTED 1
// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12285
#define SOC_CLK_TREE_SUPPORTED 1
// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32H4] IDF-12310
#define SOC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32H4] IDF-12388
@@ -536,12 +536,14 @@
#define SOC_PM_RETENTION_MODULE_NUM (32)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) // TODO: [ESP32H4] IDF-12285
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
#define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */

35
components/soc/esp32h4/register/soc/pcr_reg.h
View File

@@ -1992,21 +1992,6 @@ extern "C" {
* SYSCLK configuration register
*/
#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x114)
/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
* clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
* clock-source such as XTAL/FOSC.
*/
#define PCR_LS_DIV_NUM 0x000000FFU
#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
#define PCR_LS_DIV_NUM_V 0x000000FFU
#define PCR_LS_DIV_NUM_S 0
/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
* clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
*/
#define PCR_HS_DIV_NUM 0x000000FFU
#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
#define PCR_HS_DIV_NUM_V 0x000000FFU
#define PCR_HS_DIV_NUM_S 8
/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
* Configures to select the clock source of HP_ROOT_CLK.
* 0 (default): XTAL_CLK
@@ -2267,16 +2252,18 @@ extern "C" {
#define PCR_TIMG_CALI_CLK_SEL_S 0
/** PCR_TIMG_SECURE_CLK_SEL : R/W; bitpos: [7:4]; default: 7;
* Configures the clock source for the TIMG_SECURE_CLK.
* 0 (default):CPU_CLK
* 1: AHB_CLK
* 2: APB_CLK
* 3: sec function clock
* 4: mspi function clock
* 5: iomux function clock
* 6: parl io rx function clock
* 7: parl io tx function clock
* 8: spi2 function clock
* 0: EXT_IO_CLK
* 1: CPU_CLK
* 2: AHB_CLK
* 3: APB_CLK
* 4: sec function clock
* 5: mspi function clock
* 6: iomux function clock
* 7: parl io rx function clock
* 8: parl io tx function clock
* 9: spi3 function clock
* 10: spi2 function clock
* 11: RC_FAST_CLK
*/
#define PCR_TIMG_SECURE_CLK_SEL 0x0000000FU
#define PCR_TIMG_SECURE_CLK_SEL_M (PCR_TIMG_SECURE_CLK_SEL_V << PCR_TIMG_SECURE_CLK_SEL_S)

30
components/soc/esp32h4/register/soc/pcr_struct.h
View File

@@ -1679,15 +1679,7 @@ typedef union {
*/
typedef union {
struct {
/** ls_div_num : HRO; bitpos: [7:0]; default: 0;
* clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
* clock-source such as XTAL/FOSC.
*/
uint32_t ls_div_num:8;
/** hs_div_num : HRO; bitpos: [15:8]; default: 2;
* clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
*/
uint32_t hs_div_num:8;
uint32_t reserved_0:16;
/** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
* Configures to select the clock source of HP_ROOT_CLK.
* 0 (default): XTAL_CLK
@@ -1891,16 +1883,18 @@ typedef union {
uint32_t reserved_3:1;
/** timg_secure_clk_sel : R/W; bitpos: [7:4]; default: 7;
* Configures the clock source for the TIMG_SECURE_CLK.
* 0 (default):CPU_CLK
* 1: AHB_CLK
* 2: APB_CLK
* 3: sec function clock
* 4: mspi function clock
* 5: iomux function clock
* 6: parl io rx function clock
* 7: parl io tx function clock
* 8: spi2 function clock
* 0: EXT_IO_CLK
* 1: CPU_CLK
* 2: AHB_CLK
* 3: APB_CLK
* 4: sec function clock
* 5: mspi function clock
* 6: iomux function clock
* 7: parl io rx function clock
* 8: parl io tx function clock
* 9: spi3 function clock
* 10: spi2 function clock
* 11: RC_FAST_CLK
*/
uint32_t timg_secure_clk_sel:4;
/** timg_secure_clk_div_num : R/W; bitpos: [15:8]; default: 7;