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Driver: gpio and rtcio dirver update

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This commit is contained in:
fuzhibo
2019-06-13 15:37:58 +08:00
parent 8cd58625d0
commit 29ea0dec76
11 changed files with 637 additions and 163 deletions
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82
components/soc/esp32s2beta/include/soc/gpio_struct.h
View File

@@ -151,23 +151,14 @@ typedef volatile struct {
};
uint32_t val;
} pin[54];
uint32_t status_next; /**/
union {
struct {
uint32_t rtc_max: 10;
uint32_t reserved10: 21;
uint32_t start: 1;
uint32_t intr_st_next: 22;
uint32_t reserved22: 10;
};
uint32_t val;
} cali_conf;
union {
struct {
uint32_t value_sync2: 20;
uint32_t reserved20: 10;
uint32_t rdy_real: 1;
uint32_t rdy_sync2: 1;
};
uint32_t val;
} cali_data;
} status_next1;
union {
struct {
uint32_t func_sel: 6;
@@ -187,6 +178,71 @@ typedef volatile struct {
};
uint32_t val;
} func_out_sel_cfg[54];
union {
struct {
uint32_t clk_en: 1;
uint32_t reserved1: 31;
};
uint32_t val;
} clock_gate;
uint32_t reserved_630;
uint32_t reserved_634;
uint32_t reserved_638;
uint32_t reserved_63c;
uint32_t reserved_640;
uint32_t reserved_644;
uint32_t reserved_648;
uint32_t reserved_64c;
uint32_t reserved_650;
uint32_t reserved_654;
uint32_t reserved_658;
uint32_t reserved_65c;
uint32_t reserved_660;
uint32_t reserved_664;
uint32_t reserved_668;
uint32_t reserved_66c;
uint32_t reserved_670;
uint32_t reserved_674;
uint32_t reserved_678;
uint32_t reserved_67c;
uint32_t reserved_680;
uint32_t reserved_684;
uint32_t reserved_688;
uint32_t reserved_68c;
uint32_t reserved_690;
uint32_t reserved_694;
uint32_t reserved_698;
uint32_t reserved_69c;
uint32_t reserved_6a0;
uint32_t reserved_6a4;
uint32_t reserved_6a8;
uint32_t reserved_6ac;
uint32_t reserved_6b0;
uint32_t reserved_6b4;
uint32_t reserved_6b8;
uint32_t reserved_6bc;
uint32_t reserved_6c0;
uint32_t reserved_6c4;
uint32_t reserved_6c8;
uint32_t reserved_6cc;
uint32_t reserved_6d0;
uint32_t reserved_6d4;
uint32_t reserved_6d8;
uint32_t reserved_6dc;
uint32_t reserved_6e0;
uint32_t reserved_6e4;
uint32_t reserved_6e8;
uint32_t reserved_6ec;
uint32_t reserved_6f0;
uint32_t reserved_6f4;
uint32_t reserved_6f8;
union {
struct {
uint32_t date: 28;
uint32_t reserved28: 4;
};
uint32_t val;
} date;
} gpio_dev_t;
extern gpio_dev_t GPIO;
#ifdef __cplusplus

88
components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h
View File

@@ -13,61 +13,75 @@
// limitations under the License.
#ifndef _SOC_RTC_GPIO_CHANNEL_H
#define _SOC_RTC_GPIO_CHANNEL_H
#define _SOC_RTC_GPIO_CHANNEL_H
#define RTC_GPIO_NUMBER 22
//RTC GPIO channels
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 36
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 37
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 38
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 39
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 34
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 35
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5
#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 25
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 6
#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 26
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 7
#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8
#define RTCIO_CHANNEL_8_GPIO_NUM 33
#define RTCIO_GPIO8_CHANNEL 8 //RTCIO_CHANNEL_8
#define RTCIO_CHANNEL_8_GPIO_NUM 8
#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9
#define RTCIO_CHANNEL_9_GPIO_NUM 32
#define RTCIO_GPIO9_CHANNEL 9 //RTCIO_CHANNEL_9
#define RTCIO_CHANNEL_9_GPIO_NUM 9
#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10
#define RTCIO_CHANNEL_10_GPIO_NUM 4
#define RTCIO_GPIO10_CHANNEL 10 //RTCIO_CHANNEL_10
#define RTCIO_CHANNEL_10_GPIO_NUM 10
#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11
#define RTCIO_CHANNEL_11_GPIO_NUM 0
#define RTCIO_GPIO11_CHANNEL 11 //RTCIO_CHANNEL_11
#define RTCIO_CHANNEL_11_GPIO_NUM 11
#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12
#define RTCIO_CHANNEL_12_GPIO_NUM 2
#define RTCIO_GPIO12_CHANNEL 12 //RTCIO_CHANNEL_12
#define RTCIO_CHANNEL_12_GPIO_NUM 12
#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13
#define RTCIO_CHANNEL_13_GPIO_NUM 15
#define RTCIO_GPIO13_CHANNEL 13 //RTCIO_CHANNEL_13
#define RTCIO_CHANNEL_13_GPIO_NUM 13
#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14
#define RTCIO_CHANNEL_14_GPIO_NUM 13
#define RTCIO_GPIO14_CHANNEL 14 //RTCIO_CHANNEL_14
#define RTCIO_CHANNEL_14_GPIO_NUM 14
#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15
#define RTCIO_CHANNEL_15_GPIO_NUM 12
#define RTCIO_GPIO15_CHANNEL 15 //RTCIO_CHANNEL_15
#define RTCIO_CHANNEL_15_GPIO_NUM 15
#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16
#define RTCIO_CHANNEL_16_GPIO_NUM 14
#define RTCIO_GPIO16_CHANNEL 16 //RTCIO_CHANNEL_16
#define RTCIO_CHANNEL_16_GPIO_NUM 16
#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17
#define RTCIO_CHANNEL_17_GPIO_NUM 27
#define RTCIO_GPIO17_CHANNEL 17 //RTCIO_CHANNEL_17
#define RTCIO_CHANNEL_17_GPIO_NUM 17
#define RTCIO_GPIO18_CHANNEL 18 //RTCIO_CHANNEL_18
#define RTCIO_CHANNEL_18_GPIO_NUM 18
#define RTCIO_GPIO19_CHANNEL 19 //RTCIO_CHANNEL_19
#define RTCIO_CHANNEL_19_GPIO_NUM 19
#define RTCIO_GPIO20_CHANNEL 20 //RTCIO_CHANNEL_20
#define RTCIO_CHANNEL_20_GPIO_NUM 20
#define RTCIO_GPIO21_CHANNEL 21 //RTCIO_CHANNEL_21
#define RTCIO_CHANNEL_21_GPIO_NUM 21
#endif

118
components/soc/esp32s2beta/include/soc/rtc_io_reg.h
View File

@@ -27,7 +27,7 @@ extern "C" {
#define RTC_GPIO_OUT_DATA_V 0x3FFFFF
#define RTC_GPIO_OUT_DATA_S 10
#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x10)
#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4)
/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 output data write 1 to set*/
#define RTC_GPIO_OUT_DATA_W1TS 0x003FFFFF
@@ -35,7 +35,7 @@ extern "C" {
#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFFF
#define RTC_GPIO_OUT_DATA_W1TS_S 10
#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x20)
#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8)
/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 output data write 1 to clear*/
#define RTC_GPIO_OUT_DATA_W1TC 0x003FFFFF
@@ -43,7 +43,7 @@ extern "C" {
#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFFF
#define RTC_GPIO_OUT_DATA_W1TC_S 10
#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0x30)
#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xC)
/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 enable*/
#define RTC_GPIO_ENABLE 0x003FFFFF
@@ -51,7 +51,7 @@ extern "C" {
#define RTC_GPIO_ENABLE_V 0x3FFFFF
#define RTC_GPIO_ENABLE_S 10
#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x40)
#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10)
/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 enable write 1 to set*/
#define RTC_GPIO_ENABLE_W1TS 0x003FFFFF
@@ -59,7 +59,7 @@ extern "C" {
#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFFF
#define RTC_GPIO_ENABLE_W1TS_S 10
#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x50)
#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14)
/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 enable write 1 to clear*/
#define RTC_GPIO_ENABLE_W1TC 0x003FFFFF
@@ -67,7 +67,7 @@ extern "C" {
#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFFF
#define RTC_GPIO_ENABLE_W1TC_S 10
#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x60)
#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18)
/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 interrupt status*/
#define RTC_GPIO_STATUS_INT 0x003FFFFF
@@ -75,7 +75,7 @@ extern "C" {
#define RTC_GPIO_STATUS_INT_V 0x3FFFFF
#define RTC_GPIO_STATUS_INT_S 10
#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x70)
#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1C)
/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
#define RTC_GPIO_STATUS_INT_W1TS 0x003FFFFF
@@ -83,7 +83,7 @@ extern "C" {
#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFFF
#define RTC_GPIO_STATUS_INT_W1TS_S 10
#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x80)
#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20)
/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
#define RTC_GPIO_STATUS_INT_W1TC 0x003FFFFF
@@ -91,7 +91,7 @@ extern "C" {
#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFFF
#define RTC_GPIO_STATUS_INT_W1TC_S 10
#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x90)
#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24)
/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:10] ;default: ; */
/*description: RTC GPIO input data*/
#define RTC_GPIO_IN_NEXT 0x003FFFFF
@@ -99,7 +99,7 @@ extern "C" {
#define RTC_GPIO_IN_NEXT_V 0x3FFFFF
#define RTC_GPIO_IN_NEXT_S 10
#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0xa0)
#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28)
/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
@@ -120,7 +120,7 @@ extern "C" {
#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN0_PAD_DRIVER_S 2
#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0xb0)
#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2C)
/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
@@ -141,7 +141,7 @@ extern "C" {
#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN1_PAD_DRIVER_S 2
#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0xc0)
#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30)
/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
@@ -162,7 +162,7 @@ extern "C" {
#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN2_PAD_DRIVER_S 2
#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0xd0)
#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34)
/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
@@ -183,7 +183,7 @@ extern "C" {
#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN3_PAD_DRIVER_S 2
#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0xe0)
#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38)
/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
@@ -204,7 +204,7 @@ extern "C" {
#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN4_PAD_DRIVER_S 2
#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0xf0)
#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3C)
/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
@@ -225,7 +225,7 @@ extern "C" {
#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN5_PAD_DRIVER_S 2
#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x100)
#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40)
/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10))
@@ -246,7 +246,7 @@ extern "C" {
#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN6_PAD_DRIVER_S 2
#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x110)
#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44)
/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10))
@@ -267,7 +267,7 @@ extern "C" {
#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN7_PAD_DRIVER_S 2
#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x120)
#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48)
/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10))
@@ -288,7 +288,7 @@ extern "C" {
#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN8_PAD_DRIVER_S 2
#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x130)
#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4C)
/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10))
@@ -309,7 +309,7 @@ extern "C" {
#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN9_PAD_DRIVER_S 2
#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x140)
#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50)
/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10))
@@ -330,7 +330,7 @@ extern "C" {
#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN10_PAD_DRIVER_S 2
#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x150)
#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54)
/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10))
@@ -351,7 +351,7 @@ extern "C" {
#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN11_PAD_DRIVER_S 2
#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x160)
#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58)
/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10))
@@ -372,7 +372,7 @@ extern "C" {
#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN12_PAD_DRIVER_S 2
#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x170)
#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5C)
/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10))
@@ -393,7 +393,7 @@ extern "C" {
#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN13_PAD_DRIVER_S 2
#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x180)
#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60)
/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10))
@@ -414,7 +414,7 @@ extern "C" {
#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN14_PAD_DRIVER_S 2
#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x190)
#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64)
/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10))
@@ -435,7 +435,7 @@ extern "C" {
#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN15_PAD_DRIVER_S 2
#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x1a0)
#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68)
/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10))
@@ -456,7 +456,7 @@ extern "C" {
#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN16_PAD_DRIVER_S 2
#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x1b0)
#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6C)
/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10))
@@ -477,7 +477,7 @@ extern "C" {
#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN17_PAD_DRIVER_S 2
#define RTC_GPIO_PIN18_REG (DR_REG_RTCIO_BASE + 0x1c0)
#define RTC_GPIO_PIN18_REG (DR_REG_RTCIO_BASE + 0x70)
/* RTC_GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN18_WAKEUP_ENABLE (BIT(10))
@@ -498,7 +498,7 @@ extern "C" {
#define RTC_GPIO_PIN18_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN18_PAD_DRIVER_S 2
#define RTC_GPIO_PIN19_REG (DR_REG_RTCIO_BASE + 0x1d0)
#define RTC_GPIO_PIN19_REG (DR_REG_RTCIO_BASE + 0x74)
/* RTC_GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN19_WAKEUP_ENABLE (BIT(10))
@@ -519,7 +519,7 @@ extern "C" {
#define RTC_GPIO_PIN19_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN19_PAD_DRIVER_S 2
#define RTC_GPIO_PIN20_REG (DR_REG_RTCIO_BASE + 0x1e0)
#define RTC_GPIO_PIN20_REG (DR_REG_RTCIO_BASE + 0x78)
/* RTC_GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN20_WAKEUP_ENABLE (BIT(10))
@@ -540,7 +540,7 @@ extern "C" {
#define RTC_GPIO_PIN20_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN20_PAD_DRIVER_S 2
#define RTC_GPIO_PIN21_REG (DR_REG_RTCIO_BASE + 0x1f0)
#define RTC_GPIO_PIN21_REG (DR_REG_RTCIO_BASE + 0x7C)
/* RTC_GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
/*description: RTC GPIO wakeup enable bit*/
#define RTC_GPIO_PIN21_WAKEUP_ENABLE (BIT(10))
@@ -561,7 +561,7 @@ extern "C" {
#define RTC_GPIO_PIN21_PAD_DRIVER_V 0x1
#define RTC_GPIO_PIN21_PAD_DRIVER_S 2
#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x200)
#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x80)
/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
/*description: */
#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25))
@@ -599,7 +599,7 @@ extern "C" {
#define RTC_IO_DEBUG_SEL0_V 0x1F
#define RTC_IO_DEBUG_SEL0_S 0
#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x210)
#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x84)
/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD0_DRV 0x00000003
@@ -679,7 +679,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x220)
#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x88)
/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD1_DRV 0x00000003
@@ -759,7 +759,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x230)
#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x8C)
/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD2_DRV 0x00000003
@@ -839,7 +839,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0x240)
#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0x90)
/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD3_DRV 0x00000003
@@ -919,7 +919,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0x250)
#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0x94)
/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD4_DRV 0x00000003
@@ -999,7 +999,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0x260)
#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0x98)
/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD5_DRV 0x00000003
@@ -1079,7 +1079,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0x270)
#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0x9C)
/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD6_DRV 0x00000003
@@ -1159,7 +1159,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0x280)
#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xA0)
/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD7_DRV 0x00000003
@@ -1239,7 +1239,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0x290)
#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xA4)
/* RTC_IO_TOUCH_PAD8_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD8_DRV 0x00000003
@@ -1319,7 +1319,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD8_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD8_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0x2a0)
#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xA8)
/* RTC_IO_TOUCH_PAD9_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD9_DRV 0x00000003
@@ -1399,7 +1399,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD9_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD9_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD10_REG (DR_REG_RTCIO_BASE + 0x2b0)
#define RTC_IO_TOUCH_PAD10_REG (DR_REG_RTCIO_BASE + 0xAC)
/* RTC_IO_TOUCH_PAD10_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD10_DRV 0x00000003
@@ -1479,7 +1479,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD10_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD10_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD11_REG (DR_REG_RTCIO_BASE + 0x2c0)
#define RTC_IO_TOUCH_PAD11_REG (DR_REG_RTCIO_BASE + 0xB0)
/* RTC_IO_TOUCH_PAD11_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD11_DRV 0x00000003
@@ -1559,7 +1559,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD11_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD11_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD12_REG (DR_REG_RTCIO_BASE + 0x2d0)
#define RTC_IO_TOUCH_PAD12_REG (DR_REG_RTCIO_BASE + 0xB4)
/* RTC_IO_TOUCH_PAD12_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD12_DRV 0x00000003
@@ -1639,7 +1639,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD12_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD12_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD13_REG (DR_REG_RTCIO_BASE + 0x2e0)
#define RTC_IO_TOUCH_PAD13_REG (DR_REG_RTCIO_BASE + 0xB8)
/* RTC_IO_TOUCH_PAD13_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD13_DRV 0x00000003
@@ -1719,7 +1719,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD13_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD13_FUN_IE_S 13
#define RTC_IO_TOUCH_PAD14_REG (DR_REG_RTCIO_BASE + 0x2f0)
#define RTC_IO_TOUCH_PAD14_REG (DR_REG_RTCIO_BASE + 0xBC)
/* RTC_IO_TOUCH_PAD14_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_TOUCH_PAD14_DRV 0x00000003
@@ -1799,7 +1799,7 @@ extern "C" {
#define RTC_IO_TOUCH_PAD14_FUN_IE_V 0x1
#define RTC_IO_TOUCH_PAD14_FUN_IE_S 13
#define RTC_IO_XTAL_32P_PAD_REG (DR_REG_RTCIO_BASE + 0x300)
#define RTC_IO_XTAL_32P_PAD_REG (DR_REG_RTCIO_BASE + 0xC0)
/* RTC_IO_X32P_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_X32P_DRV 0x00000003
@@ -1855,7 +1855,7 @@ extern "C" {
#define RTC_IO_X32P_FUN_IE_V 0x1
#define RTC_IO_X32P_FUN_IE_S 13
#define RTC_IO_XTAL_32N_PAD_REG (DR_REG_RTCIO_BASE + 0x310)
#define RTC_IO_XTAL_32N_PAD_REG (DR_REG_RTCIO_BASE + 0xC4)
/* RTC_IO_X32N_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_X32N_DRV 0x00000003
@@ -1911,7 +1911,7 @@ extern "C" {
#define RTC_IO_X32N_FUN_IE_V 0x1
#define RTC_IO_X32N_FUN_IE_S 13
#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0x320)
#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0xC8)
/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: PDAC1_DRV*/
#define RTC_IO_PDAC1_DRV 0x00000003
@@ -1986,7 +1986,7 @@ extern "C" {
#define RTC_IO_PDAC1_DAC_V 0xFF
#define RTC_IO_PDAC1_DAC_S 3
#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0x330)
#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0xCC)
/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: PDAC2_DRV*/
#define RTC_IO_PDAC2_DRV 0x00000003
@@ -2061,7 +2061,7 @@ extern "C" {
#define RTC_IO_PDAC2_DAC_V 0xFF
#define RTC_IO_PDAC2_DAC_S 3
#define RTC_IO_RTC_PAD19_REG (DR_REG_RTCIO_BASE + 0x340)
#define RTC_IO_RTC_PAD19_REG (DR_REG_RTCIO_BASE + 0xD0)
/* RTC_IO_PAD19_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_PAD19_DRV 0x00000003
@@ -2117,7 +2117,7 @@ extern "C" {
#define RTC_IO_PAD19_FUN_IE_V 0x1
#define RTC_IO_PAD19_FUN_IE_S 13
#define RTC_IO_RTC_PAD20_REG (DR_REG_RTCIO_BASE + 0x350)
#define RTC_IO_RTC_PAD20_REG (DR_REG_RTCIO_BASE + 0xD4)
/* RTC_IO_PAD20_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_PAD20_DRV 0x00000003
@@ -2173,7 +2173,7 @@ extern "C" {
#define RTC_IO_PAD20_FUN_IE_V 0x1
#define RTC_IO_PAD20_FUN_IE_S 13
#define RTC_IO_RTC_PAD21_REG (DR_REG_RTCIO_BASE + 0x360)
#define RTC_IO_RTC_PAD21_REG (DR_REG_RTCIO_BASE + 0xD8)
/* RTC_IO_PAD21_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
/*description: DRV*/
#define RTC_IO_PAD21_DRV 0x00000003
@@ -2229,7 +2229,7 @@ extern "C" {
#define RTC_IO_PAD21_FUN_IE_V 0x1
#define RTC_IO_PAD21_FUN_IE_S 13
#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0x370)
#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xDC)
/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
/*description: */
#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F
@@ -2237,7 +2237,7 @@ extern "C" {
#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F
#define RTC_IO_EXT_WAKEUP0_SEL_S 27
#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0x380)
#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xE0)
/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
/*description: select RTC GPIO 0 ~ 17 to control XTAL*/
#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F
@@ -2245,7 +2245,7 @@ extern "C" {
#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F
#define RTC_IO_XTL_EXT_CTR_SEL_S 27
#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0x390)
#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xE4)
/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
/*description: */
#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003
@@ -2265,8 +2265,8 @@ extern "C" {
#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F
#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23
#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x7f0)
/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1808030 ; */
#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1FC)
/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1903170 ; */
/*description: */
#define RTC_IO_IO_DATE 0x0FFFFFFF
#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))

13
components/soc/esp32s2beta/include/soc/rtc_io_struct.h
View File

@@ -98,18 +98,7 @@ typedef volatile struct {
uint32_t reserved11: 21;
};
uint32_t val;
} pin[21];
union {
struct {
uint32_t reserved0: 2;
uint32_t rtc_gpio_pin21_pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
uint32_t reserved3: 4;
uint32_t rtc_gpio_pin21_int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
uint32_t rtc_gpio_pin21_wakeup_enable: 1; /*RTC GPIO wakeup enable bit*/
uint32_t reserved11: 21;
};
uint32_t val;
} pin21;
} pin[22];
union {
struct {
uint32_t sel0: 5;

29
components/soc/esp32s2beta/rtc_periph.c
View File

@@ -14,7 +14,28 @@
#include "soc/rtc_periph.h"
//Reg,Mux,Fun,IE,Up,Down,Rtc_number
const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = {
0
};
/* Reg,Mux,Fun,IE,Up,Down,Rtc_number */
rtc_gpio_info_t* rtc_gpio_reg[RTC_GPIO_NUMBER] = {
(rtc_gpio_info_t*)&RTCIO.touch_pad[0].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[1].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[2].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[3].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[4].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[5].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[6].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[7].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[8].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[9].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[10].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[11].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[12].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[13].val,
(rtc_gpio_info_t*)&RTCIO.touch_pad[14].val,
(rtc_gpio_info_t*)&RTCIO.xtal_32p_pad.val,
(rtc_gpio_info_t*)&RTCIO.xtal_32n_pad.val,
(rtc_gpio_info_t*)&RTCIO.pad_dac[0].val,
(rtc_gpio_info_t*)&RTCIO.pad_dac[1].val,
(rtc_gpio_info_t*)&RTCIO.rtc_pad19.val,
(rtc_gpio_info_t*)&RTCIO.rtc_pad20.val,
(rtc_gpio_info_t*)&RTCIO.rtc_pad21.val
};

4
components/soc/esp32s2beta/sources.cmake
View File

@@ -5,7 +5,9 @@ set(SOC_SRCS "cpu_util.c"
"rtc_sleep.c"
"rtc_time.c"
"soc_memory_layout.c"
"spi_periph.c")
"spi_periph.c"
"gpio_periph.c"
"rtc_periph.c")
if(NOT CMAKE_BUILD_EARLY_EXPANSION)
set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES