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Support ESP32S3 Beta 3 target

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Update ROM API. Port changes from bringup branch.
This commit is contained in:
Marius Vikhammer
2021-03-17 18:48:05 +08:00
parent e2919eca8e
commit 2aead8ba57
58 changed files with 5112 additions and 2552 deletions
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124
components/hal/esp32s3/include/hal/gdma_ll.h
View File

@@ -50,11 +50,11 @@ extern "C" {
*/
static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].mem_trans_en = enable;
dev->in[channel].conf0.mem_trans_en = enable;
if (enable) {
// to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value
dev->peri_sel[channel].peri_in_sel = 0;
dev->peri_sel[channel].peri_out_sel = 0;
dev->in[channel].peri_sel.sel = 0;
dev->out[channel].peri_sel.sel = 0;
}
}
@@ -63,7 +63,7 @@ static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bo
*/
static inline uint32_t gdma_ll_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
{
return dev->int_st[channel].val;
return dev->in[channel].int_st.val;
}
/**
@@ -72,9 +72,9 @@ static inline uint32_t gdma_ll_get_interrupt_status(gdma_dev_t *dev, uint32_t ch
static inline void gdma_ll_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
if (enable) {
dev->int_ena[channel].val |= mask;
dev->in[channel].int_ena.val |= mask;
} else {
dev->int_ena[channel].val &= ~mask;
dev->in[channel].int_ena.val &= ~mask;
}
}
@@ -83,7 +83,7 @@ static inline void gdma_ll_enable_interrupt(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
{
dev->int_clr[channel].val = mask;
dev->in[channel].int_clr.val = mask;
}
/**
@@ -100,7 +100,7 @@ static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
*/
static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf1[channel].check_owner = enable;
dev->in[channel].conf1.in_check_owner = enable;
}
/**
@@ -108,7 +108,7 @@ static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].in_data_burst_en = enable;
dev->in[channel].conf0.in_data_burst_en = enable;
}
/**
@@ -116,7 +116,7 @@ static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channe
*/
static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].indscr_burst_en = enable;
dev->in[channel].conf0.indscr_burst_en = enable;
}
/**
@@ -124,8 +124,8 @@ static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t
*/
static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
dev->conf0[channel].in_rst = 1;
dev->conf0[channel].in_rst = 0;
dev->in[channel].conf0.in_rst = 1;
dev->in[channel].conf0.in_rst = 0;
}
/**
@@ -134,7 +134,7 @@ static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
dev->conf1[channel].in_ext_mem_bk_size = size_index;
dev->in[channel].conf1.in_ext_mem_bk_size = size_index;
}
/**
@@ -142,7 +142,7 @@ static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha
*/
static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel, uint32_t water_mark)
{
dev->conf1[channel].infifo_full_thrs = water_mark;
dev->in[channel].conf1.dma_infifo_full_thrs = water_mark;
}
/**
@@ -151,7 +151,7 @@ static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel,
*/
static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->infifo_status[channel].val & (1 << 2 * (fifo_level - 1));
return dev->in[channel].infifo_status.val & (1 << 2 * (fifo_level - 1));
}
/**
@@ -160,7 +160,7 @@ static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->infifo_status[channel].val & (1 << (2 * (fifo_level - 1) + 1));
return dev->in[channel].infifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
}
/**
@@ -171,11 +171,11 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
{
switch (fifo_level) {
case 1:
return dev->infifo_status[channel].infifo_cnt_l1;
return dev->in[channel].infifo_status.infifo_cnt_l1;
case 2:
return dev->infifo_status[channel].infifo_cnt_l2;
return dev->in[channel].infifo_status.infifo_cnt_l2;
case 3:
return dev->infifo_status[channel].infifo_cnt_l3;
return dev->in[channel].infifo_status.infifo_cnt_l3;
}
}
@@ -184,8 +184,8 @@ static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
*/
static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
{
dev->in_pop[channel].infifo_pop = 1;
return dev->in_pop[channel].infifo_rdata;
dev->in[channel].pop.infifo_pop = 1;
return dev->in[channel].pop.infifo_rdata;
}
/**
@@ -193,7 +193,7 @@ static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
dev->in_link[channel].addr = addr;
dev->in[channel].link.addr = addr;
}
/**
@@ -201,7 +201,7 @@ static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
{
dev->in_link[channel].start = 1;
dev->in[channel].link.start = 1;
}
/**
@@ -209,7 +209,7 @@ static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->in_link[channel].stop = 1;
dev->in[channel].link.stop = 1;
}
/**
@@ -217,7 +217,7 @@ static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
{
dev->in_link[channel].restart = 1;
dev->in[channel].link.restart = 1;
}
/**
@@ -225,7 +225,7 @@ static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in_link[channel].auto_ret = enable;
dev->in[channel].link.auto_ret = enable;
}
/**
@@ -233,7 +233,7 @@ static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t chann
*/
static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_link[channel].park;
return dev->in[channel].link.park;
}
/**
@@ -241,7 +241,7 @@ static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
*/
static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_suc_eof_des_addr[channel];
return dev->in[channel].suc_eof_des_addr;
}
/**
@@ -249,7 +249,7 @@ static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uin
*/
static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_err_eof_des_addr[channel];
return dev->in[channel].err_eof_des_addr;
}
/**
@@ -257,7 +257,7 @@ static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint3
*/
static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->in_dscr[channel];
return dev->in[channel].dscr;
}
/**
@@ -265,7 +265,7 @@ static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_
*/
static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->wight[channel].rx_weight = weight;
dev->in[channel].wight.rx_weight = weight;
}
/**
@@ -273,15 +273,15 @@ static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint
*/
static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->pri[channel].rx_pri = prio;
dev->in[channel].pri.rx_pri = prio;
}
/**
* @brief Connect DMA RX channel to a given peripheral
*/
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, uint32_t periph_id)
{
dev->peri_sel[channel].peri_in_sel = periph_id;
dev->in[channel].peri_sel.sel = periph_id;
}
/**
@@ -292,7 +292,7 @@ static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->sram_size[channel].in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
dev->in[channel].sram_size.in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}
@@ -303,7 +303,7 @@ static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t c
*/
static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf1[channel].check_owner = enable;
dev->out[channel].conf1.out_check_owner = enable;
}
/**
@@ -311,7 +311,7 @@ static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].out_data_burst_en = enable;
dev->out[channel].conf0.out_data_burst_en = enable;
}
/**
@@ -319,7 +319,7 @@ static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channe
*/
static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].outdscr_burst_en = enable;
dev->out[channel].conf0.outdscr_burst_en = enable;
}
/**
@@ -327,7 +327,7 @@ static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t
*/
static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
{
dev->conf0[channel].out_eof_mode = mode;
dev->out[channel].conf0.out_eof_mode = mode;
}
/**
@@ -335,7 +335,7 @@ static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf0[channel].out_auto_wrback = enable;
dev->out[channel].conf0.out_auto_wrback = enable;
}
/**
@@ -343,8 +343,8 @@ static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t c
*/
static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
{
dev->conf0[channel].out_rst = 1;
dev->conf0[channel].out_rst = 0;
dev->out[channel].conf0.out_rst = 1;
dev->out[channel].conf0.out_rst = 0;
}
/**
@@ -353,7 +353,7 @@ static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
dev->conf1[channel].out_ext_mem_bk_size = size_index;
dev->out[channel].conf1.out_ext_mem_bk_size = size_index;
}
/**
@@ -362,7 +362,7 @@ static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t cha
*/
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->outfifo_status[channel].val & (1 << 2 * (fifo_level - 1));
return dev->out[channel].outfifo_status.val & (1 << 2 * (fifo_level - 1));
}
/**
@@ -371,7 +371,7 @@ static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, ui
*/
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
{
return dev->outfifo_status[channel].val & (1 << (2 * (fifo_level - 1) + 1));
return dev->out[channel].outfifo_status.val & (1 << (2 * (fifo_level - 1) + 1));
}
/**
@@ -382,11 +382,11 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
{
switch (fifo_level) {
case 1:
return dev->outfifo_status[channel].outfifo_cnt_l1;
return dev->out[channel].outfifo_status.outfifo_cnt_l1;
case 2:
return dev->outfifo_status[channel].outfifo_cnt_l2;
return dev->out[channel].outfifo_status.outfifo_cnt_l2;
case 3:
return dev->outfifo_status[channel].outfifo_cnt_l3;
return dev->out[channel].outfifo_status.outfifo_cnt_l3;
}
}
@@ -395,8 +395,8 @@ static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t chann
*/
static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
{
dev->out_push[channel].outfifo_wdata = data;
dev->out_push[channel].outfifo_push = 1;
dev->out[channel].push.outfifo_wdata = data;
dev->out[channel].push.outfifo_push = 1;
}
/**
@@ -404,7 +404,7 @@ static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint3
*/
static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
{
dev->out_link[channel].addr = addr;
dev->out[channel].link.addr = addr;
}
/**
@@ -412,7 +412,7 @@ static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, u
*/
static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
{
dev->out_link[channel].start = 1;
dev->out[channel].link.start = 1;
}
/**
@@ -420,7 +420,7 @@ static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
{
dev->out_link[channel].stop = 1;
dev->out[channel].link.stop = 1;
}
/**
@@ -428,7 +428,7 @@ static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
*/
static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
{
dev->out_link[channel].restart = 1;
dev->out[channel].link.restart = 1;
}
/**
@@ -436,7 +436,7 @@ static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
*/
static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
{
return dev->out_link[channel].park;
return dev->out[channel].link.park;
}
/**
@@ -444,7 +444,7 @@ static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
*/
static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->out_eof_des_addr[channel];
return dev->out[channel].eof_des_addr;
}
/**
@@ -452,7 +452,7 @@ static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t ch
*/
static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
{
return dev->out_dscr[channel];
return dev->out[channel].dscr;
}
/**
@@ -460,7 +460,7 @@ static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_
*/
static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->wight[channel].tx_weight = weight;
dev->out[channel].wight.tx_weight = weight;
}
/**
@@ -468,15 +468,15 @@ static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint
*/
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->pri[channel].tx_pri = prio;
dev->out[channel].pri.tx_pri = prio;
}
/**
* @brief Connect DMA TX channel to a given peripheral
*/
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, int periph_id)
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, uint32_t periph_id)
{
dev->peri_sel[channel].peri_out_sel = periph_id;
dev->out[channel].peri_sel.sel = periph_id;
}
/**
@@ -487,7 +487,7 @@ static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
static inline void gdma_ll_tx_extend_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->sram_size[channel].out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
dev->out[channel].sram_size.out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}

14
components/hal/esp32s3/include/hal/i2c_ll.h
View File

@@ -90,6 +90,8 @@ typedef struct {
#define I2C_LL_SLAVE_RX_INT (I2C_RXFIFO_WM_INT_ENA_M | I2C_TRANS_COMPLETE_INT_ENA_M)
// I2C source clock
#define I2C_LL_CLK_SRC_FREQ(src_clk) (((src_clk) == I2C_SCLK_RTC) ? 8*1000*1000 : 40*1000*1000); // Another clock is XTAL clock
// I2C max timeout value
#define I2C_LL_MAX_TIMEOUT I2C_TIME_OUT_VALUE_V
/**
* @brief Calculate I2C bus frequency
@@ -159,7 +161,7 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
//hold
hw->scl_start_hold.time = bus_cfg->hold - 1;
hw->scl_stop_hold.time = bus_cfg->hold;
hw->timeout.time_out_value = bus_cfg->tout;
hw->timeout.tout = bus_cfg->tout;
hw->timeout.time_out_en = 1;
}
@@ -280,7 +282,7 @@ static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
*/
static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
{
hw->timeout.time_out_value = tout;
hw->timeout.tout = tout;
}
/**
@@ -449,7 +451,7 @@ static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw)
*/
static inline bool i2c_ll_is_bus_busy(i2c_dev_t *hw)
{
return hw->status_reg.bus_busy;
return hw->sr.bus_busy;
}
/**
@@ -473,7 +475,7 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw)
*/
static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
{
return hw->status_reg.rx_fifo_cnt;
return hw->sr.rx_fifo_cnt;
}
/**
@@ -485,7 +487,7 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw)
*/
static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
{
return SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt;
return SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt;
}
/**
@@ -497,7 +499,7 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw)
*/
static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw)
{
return hw->timeout.time_out_value;
return hw->timeout.tout;
}
/**

8
components/hal/esp32s3/include/hal/rmt_ll.h
View File

@@ -88,16 +88,16 @@ static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_conf[channel].mem_rd_rst = 1;
dev->tx_conf[channel].mem_rd_rst = 0;
dev->tx_conf[channel].apb_mem_rst = 1;
dev->tx_conf[channel].apb_mem_rst = 0;
dev->tx_conf[channel].mem_rst = 1;
dev->tx_conf[channel].mem_rst = 0;
}
static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->rx_conf[channel].conf1.mem_wr_rst = 1;
dev->rx_conf[channel].conf1.mem_wr_rst = 0;
dev->rx_conf[channel].conf1.apb_mem_rst = 1;
dev->rx_conf[channel].conf1.apb_mem_rst = 0;
dev->rx_conf[channel].conf1.mem_rst = 1;
dev->rx_conf[channel].conf1.mem_rst = 0;
}
static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel)

6
components/hal/esp32s3/include/hal/touch_sensor_ll.h
View File

@@ -745,9 +745,9 @@ static inline void touch_ll_filter_get_debounce(uint32_t *dbc_cnt)
static inline void touch_ll_filter_set_noise_thres(uint32_t noise_thr)
{
RTCCNTL.touch_filter_ctrl.touch_noise_thres = noise_thr;
RTCCNTL.touch_filter_ctrl.config2 = noise_thr;
RTCCNTL.touch_filter_ctrl.config1 = 0xF;
RTCCNTL.touch_filter_ctrl.config3 = 2;
RTCCNTL.touch_filter_ctrl.touch_neg_noise_thres = noise_thr;
RTCCNTL.touch_filter_ctrl.touch_neg_noise_limit = 0xF;
RTCCNTL.touch_filter_ctrl.touch_hysteresis = 2;
}
/**