alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-25 17:58:46 +00:00
Code Issues Packages Projects Releases Wiki Activity

refactor(clk): add soc_clk_calibration_clk_src_t for all targets

Browse Source 
Cleaned up RTC calibration clock selection code
This commit is contained in:
Song Ruo Jing
2025-07-21 22:00:00 +08:00
parent 07120c1d38
commit 2b01b7c6f8
54 changed files with 786 additions and 495 deletions
Download Patch File Download Diff File Expand all files Collapse all files

66
components/hal/esp32c5/include/hal/clk_tree_ll.h
View File

@@ -441,6 +441,55 @@ static inline __attribute__((always_inline)) void clk_ll_soc_root_clk_auto_gatin
}
}
/**
* @brief Enable the RTC clock calibration reference XTAL source on timer group0.
* @param enable Enable or disable the XTAL source.
*/
static inline __attribute__((always_inline)) void clk_ll_enable_timergroup_rtc_calibration_clock(bool enable)
{
PCR.timergroup_xtal_conf.tg0_xtal_clk_en = enable;
}
/**
* @brief Select the calibration clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
switch (clk_sel) {
case CLK_CAL_32K_XTAL:
timg_cali_clk_sel = 1;
break;
case CLK_CAL_32K_OSC_SLOW:
timg_cali_clk_sel = 2;
break;
case CLK_CAL_RC_SLOW:
timg_cali_clk_sel = 3;
break;
case CLK_CAL_RC_FAST:
timg_cali_clk_sel = 4;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
if (timg_cali_clk_sel >= 0) {
PCR.ctrl_32k_conf.clk_32k_sel = timg_cali_clk_sel;
}
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/**
* @brief Select the clock source for RTC_SLOW_CLK
*
@@ -549,14 +598,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider
return 1;
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/**
* @brief Set RC_SLOW_CLK divider
*
@@ -568,15 +609,6 @@ static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uin
HAL_ASSERT(divider == 1);
}
/**
* @brief Enable the RTC clock calibration reference XTAL source on timer group0.
* @param enable enable or disable the XTAL source.
*/
static inline __attribute__((always_inline)) void clk_ll_enable_timergroup_rtc_calibration_clock(bool enable)
{
PCR.timergroup_xtal_conf.tg0_xtal_clk_en = enable;
}
/************************** LP STORAGE REGISTER STORE/LOAD **************************/
/**
* @brief Store RTC_SLOW_CLK calibration value in RTC storage register