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refactor(clk): add soc_clk_calibration_clk_src_t for all targets

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Cleaned up RTC calibration clock selection code
This commit is contained in:
Song Ruo Jing
2025-07-21 22:00:00 +08:00
parent 07120c1d38
commit 2b01b7c6f8
54 changed files with 786 additions and 495 deletions
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48
components/hal/esp32c61/include/hal/clk_tree_ll.h
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@@ -396,6 +396,46 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_apb_get_divider(voi
return HAL_FORCE_READ_U32_REG_FIELD(PCR.apb_freq_conf, apb_div_num) + 1;
}
/**
* @brief Select the calibration clock source for timergroup0
*
* @param clk_sel One of the clock sources in soc_timg0_calibration_clk_src_t
*/
static inline __attribute__((always_inline)) void clk_ll_calibration_set_target(soc_timg0_calibration_clk_src_t clk_sel)
{
int timg_cali_clk_sel = -1;
switch (clk_sel) {
case CLK_CAL_32K_XTAL:
timg_cali_clk_sel = 1;
break;
case CLK_CAL_32K_OSC_SLOW:
timg_cali_clk_sel = 2;
break;
case CLK_CAL_RC_SLOW:
timg_cali_clk_sel = 3;
break;
case CLK_CAL_RC_FAST:
timg_cali_clk_sel = 4;
break;
default:
// Unsupported CLK_CAL mux input
abort();
}
if (timg_cali_clk_sel >= 0) {
PCR.ctrl_32k_conf.clk_32k_sel = timg_cali_clk_sel;
}
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline __attribute__((always_inline)) void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/**
* @brief Select the clock source for RTC_SLOW_CLK
*
@@ -504,14 +544,6 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_rc_fast_get_divider
return 1;
}
/**
* @brief Set the frequency division factor of RC_FAST clock
*/
static inline void clk_ll_rc_fast_tick_conf(void)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.ctrl_32k_conf, fosc_tick_num, (1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS) - 1); // divider = 1 << CLK_LL_RC_FAST_CALIB_TICK_DIV_BITS
}
/**
* @brief Set RC_SLOW_CLK divider
*