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refactor(clk): add soc_clk_calibration_clk_src_t for all targets

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Cleaned up RTC calibration clock selection code
This commit is contained in:
Song Ruo Jing
2025-07-21 22:00:00 +08:00
parent 07120c1d38
commit 2b01b7c6f8
54 changed files with 786 additions and 495 deletions
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10
components/soc/esp32/include/soc/clk_tree_defs.h
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@@ -484,6 +484,16 @@ typedef enum {
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
/**
* @brief Clock frequency calibration source selection
*/
typedef enum {
CLK_CAL_RTC_SLOW, /*!< Select to calibrate RTC_SLOW_CLK */
CLK_CAL_RC_FAST_D256, /*!< Select to calibrate RC_FAST_D256_CLK */
CLK_CAL_32K_XTAL, /*!< Select to calibrate XTAL32K_CLK */
} soc_timg0_calibration_clk_src_t;
#ifdef __cplusplus
}
#endif

2
components/soc/esp32/register/soc/timer_group_struct.h
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@@ -347,7 +347,7 @@ typedef union {
*/
uint32_t rtc_cali_start_cycling: 1;
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
* 0:rtcslowclock. 1:clk_80m. 2:xtal_32k.
* 0:rtc_slow_clock. 1:rc_fast_div_clk. 2:xtal_32k.
*/
uint32_t rtc_cali_clk_sel: 2;
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;