refactor(clk): add soc_clk_calibration_clk_src_t for all targets

Cleaned up RTC calibration clock selection code

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -516,6 +516,18 @@ typedef enum {
     CLKOUT_SIG_INVALID  = 0xFF,
 } soc_clkout_sig_id_t;
 
+////////////////////////////////////////////RTC CALIBRATION///////////////////////////////////////////////////////////
+/**
+ * @brief Clock frequency calibration source selection
+ */
+typedef enum {
+    CLK_CAL_RC_SLOW = 0,                             /*!< Select to calibrate RC_SLOW_CLK */
+    CLK_CAL_RC32K,                                   /*!< Select to calibrate RC32K_CLK */
+    CLK_CAL_32K_XTAL,                                /*!< Select to calibrate XTAL32K_CLK */
+    CLK_CAL_32K_OSC_SLOW,                            /*!< Select to calibrate OSC_SLOW_CLK (external slow clock) */
+    CLK_CAL_RC_FAST,                                 /*!< Select to calibrate RC_FAST_CLK */
+} soc_timg0_calibration_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c6/register/soc/timer_group_struct.h

@@ -339,7 +339,7 @@ typedef union {
          */
         uint32_t rtc_cali_start_cycling:1;
         /** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
-         *  0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
+         *  0/3:rc_slow_clk. 1:rc_fast_div_clk, 2:32k clock, which 32k depends on PCR.ctrl_32k_conf.clk_32k_sel.
          */
         uint32_t rtc_cali_clk_sel:2;
         /** rtc_cali_rdy : RO; bitpos: [15]; default: 0;