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feat(esp32c5): support esp32c5 g0 components

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This commit is contained in:
laokaiyao
2023-12-05 15:38:55 +08:00
parent 8eee6529dd
commit 2b44d62e43
47 changed files with 5498 additions and 302 deletions
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48
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in Normal file
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@@ -0,0 +1,48 @@
#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_INT_HW_NESTED_SUPPORTED
bool
default y
config SOC_CPU_CORES_NUM
int
default 1
config SOC_INT_CLIC_SUPPORTED
bool
default y
config SOC_GPIO_PIN_COUNT
int
default 31
config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_TIMER_GROUPS
int
default 2
config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 1
config SOC_UART_NUM
int
default 3
config SOC_UART_HP_NUM
int
default 2
config SOC_UART_LP_NUM
int
default 1

50
components/soc/esp32c5/include/soc/apb_saradc_reg.h
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@@ -14,7 +14,7 @@ extern "C" {
/** APB_SARADC_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0)
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
* select software enable saradc sample
*/
@@ -82,7 +82,7 @@ extern "C" {
/** APB_SARADC_CTRL2_REG register
* digital saradc configure register
*/
#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4)
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
* enable max meas num
*/
@@ -129,7 +129,7 @@ extern "C" {
/** APB_SARADC_FILTER_CTRL1_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8)
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
/** APB_SARADC_APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
* Factor of saradc filter1
*/
@@ -148,7 +148,7 @@ extern "C" {
/** APB_SARADC_SAR_PATT_TAB1_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18)
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
* item 0 ~ 3 for pattern table 1 (each item one byte)
*/
@@ -160,7 +160,7 @@ extern "C" {
/** APB_SARADC_SAR_PATT_TAB2_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c)
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c)
/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
* Item 4 ~ 7 for pattern table 1 (each item one byte)
*/
@@ -172,7 +172,7 @@ extern "C" {
/** APB_SARADC_ONETIME_SAMPLE_REG register
* digital saradc configure register
*/
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20)
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20)
/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
* configure onetime atten
*/
@@ -212,7 +212,7 @@ extern "C" {
/** APB_SARADC_ARB_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24)
#define APB_SARADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24)
/** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
* adc2 arbiter force to enableapb controller
*/
@@ -273,7 +273,7 @@ extern "C" {
/** APB_SARADC_FILTER_CTRL0_REG register
* digital saradc configure register
*/
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28)
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28)
/** APB_SARADC_APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
* configure filter1 to adc channel
*/
@@ -299,7 +299,7 @@ extern "C" {
/** APB_SARADC_SAR1DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c)
#define APB_SARADC_SAR1DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c)
/** APB_SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
* saradc1 data
*/
@@ -311,7 +311,7 @@ extern "C" {
/** APB_SARADC_SAR2DATA_STATUS_REG register
* digital saradc configure register
*/
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_BASE + 0x30)
#define APB_SARADC_SAR2DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30)
/** APB_SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
* saradc2 data
*/
@@ -323,7 +323,7 @@ extern "C" {
/** APB_SARADC_THRES0_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34)
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34)
/** APB_SARADC_APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres0 to adc channel
*/
@@ -349,7 +349,7 @@ extern "C" {
/** APB_SARADC_THRES1_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38)
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
/** APB_SARADC_APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
* configure thres1 to adc channel
*/
@@ -375,7 +375,7 @@ extern "C" {
/** APB_SARADC_THRES_CTRL_REG register
* digital saradc configure register
*/
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c)
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c)
/** APB_SARADC_APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
* enable thres to all channel
*/
@@ -401,7 +401,7 @@ extern "C" {
/** APB_SARADC_INT_ENA_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40)
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40)
/** APB_SARADC_APB_SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
* tsens low interrupt enable
*/
@@ -455,7 +455,7 @@ extern "C" {
/** APB_SARADC_INT_RAW_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44)
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44)
/** APB_SARADC_APB_SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
* saradc tsens interrupt raw
*/
@@ -509,7 +509,7 @@ extern "C" {
/** APB_SARADC_INT_ST_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48)
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48)
/** APB_SARADC_APB_SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
* saradc tsens interrupt state
*/
@@ -563,7 +563,7 @@ extern "C" {
/** APB_SARADC_INT_CLR_REG register
* digital saradc int register
*/
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c)
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c)
/** APB_SARADC_APB_SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
* saradc tsens interrupt clear
*/
@@ -617,7 +617,7 @@ extern "C" {
/** APB_SARADC_DMA_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50)
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50)
/** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
*/
@@ -643,7 +643,7 @@ extern "C" {
/** APB_SARADC_CLKM_CONF_REG register
* digital saradc configure register
*/
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54)
#define APB_SARADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54)
/** APB_SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
* Integral I2S clock divider value
*/
@@ -683,7 +683,7 @@ extern "C" {
/** APB_SARADC_APB_TSENS_CTRL_REG register
* digital tsens configure register
*/
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58)
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
/** APB_SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
* temperature sensor data out
*/
@@ -716,7 +716,7 @@ extern "C" {
/** APB_SARADC_TSENS_CTRL2_REG register
* digital tsens configure register
*/
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c)
#define APB_SARADC_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c)
/** APB_SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
* tsens clk select
*/
@@ -728,7 +728,7 @@ extern "C" {
/** APB_SARADC_CALI_REG register
* digital saradc configure register
*/
#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60)
#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60)
/** APB_SARADC_APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
* saradc cali factor
*/
@@ -740,7 +740,7 @@ extern "C" {
/** APB_TSENS_WAKE_REG register
* digital tsens configure register
*/
#define APB_TSENS_WAKE_REG (DR_REG_APB_BASE + 0x64)
#define APB_TSENS_WAKE_REG (DR_REG_APB_SARADC_BASE + 0x64)
/** APB_SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
* reg_wakeup_th_low
*/
@@ -780,7 +780,7 @@ extern "C" {
/** APB_TSENS_SAMPLE_REG register
* digital tsens configure register
*/
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_BASE + 0x68)
#define APB_TSENS_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x68)
/** APB_SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
* HW sample rate
*/
@@ -799,7 +799,7 @@ extern "C" {
/** APB_SARADC_CTRL_DATE_REG register
* version
*/
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc)
#define APB_SARADC_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
/** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
* version
*/

108
components/soc/esp32c5/include/soc/clic_reg.h Normal file
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@@ -0,0 +1,108 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define NLBITS 3
#define CLIC_EXT_INTR_NUM_OFFSET 16
#define DUALCORE_CLIC_CTRL_OFF 0x10000
#define DR_REG_CLIC_BASE ( 0x20800000 )
#define DR_REG_CLIC_CTRL_BASE ( 0x20801000 )
#define CLIC_INT_CONFIG_REG (DR_REG_CLIC_BASE + 0x0)
/* CLIC_INT_CONFIG_NMBITS : R/W ;bitpos:[6:5] ;default: 2'd0 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NMBITS 0x00000003
#define CLIC_INT_CONFIG_NMBITS_M ((CLIC_INT_CONFIG_NMBITS_V)<<(CLIC_INT_CONFIG_NMBITS_S))
#define CLIC_INT_CONFIG_NMBITS_V 0x3
#define CLIC_INT_CONFIG_NMBITS_S 5
/* CLIC_INT_CONFIG_NLBITS : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NLBITS 0x0000000F
#define CLIC_INT_CONFIG_NLBITS_M ((CLIC_INT_CONFIG_NLBITS_V)<<(CCLIC_INT_CONFIG_NLBITS_S))
#define CLIC_INT_CONFIG_NLBITS_V 0xF
#define CLIC_INT_CONFIG_NLBITS_S 1
/* CLIC_INT_CONFIG_NVBITS : R/W ;bitpos:[0] ;default: 1'd1 ; */
/*description: .*/
#define CLIC_INT_CONFIG_NVBITS (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_M (BIT(0))
#define CLIC_INT_CONFIG_NVBITS_V 0x1
#define CLIC_INT_CONFIG_NVBITS_S 0
#define CLIC_INT_INFO_REG (DR_REG_CLIC_BASE + 0x4)
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[24:21] ;default: 4'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_CTLBITS 0x0000000F
#define CLIC_INT_INFO_CTLBITS_M ((CLIC_INT_INFO_CTLBITS_V)<<(CLIC_INT_INFO_CTLBITS_S))
#define CLIC_INT_INFO_CTLBITS_V 0xF
#define CLIC_INT_INFO_CTLBITS_S 21
/* CLIC_INT_INFO_VERSION : R/W ;bitpos:[20:13] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_VERSION 0x000000FF
#define CLIC_INT_INFO_VERSION_M ((CLIC_INT_INFO_VERSION_V)<<(CLIC_INT_INFO_VERSION_S))
#define CLIC_INT_INFO_VERSION_V 0xFF
#define CLIC_INT_INFO_VERSION_S 13
/* CLIC_INT_INFO_NUM_INT : R/W ;bitpos:[12:0] ;default: 13'd0 ; */
/*description: .*/
#define CLIC_INT_INFO_NUM_INT 0x00001FFF
#define CLIC_INT_INFO_NUM_INT_M ((CLIC_INT_INFO_NUM_INT_V)<<(CLIC_INT_INFO_NUM_INT_S))
#define CLIC_INT_INFO_NUM_INT_V 0x1FFF
#define CLIC_INT_INFO_NUM_INT_S 0
#define CLIC_INT_THRESH_REG (DR_REG_CLIC_BASE + 0x8)
/* CLIC_CPU_INT_THRESH : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_CPU_INT_THRESH 0x000000FF
#define CLIC_CPU_INT_THRESH_M ((CLIC_CPU_INT_THRESH_V)<<(CLIC_CPU_INT_THRESH_S))
#define CLIC_CPU_INT_THRESH_V 0xFF
#define CLIC_CPU_INT_THRESH_S 24
#define CLIC_INT_CTRL_REG(i) (DR_REG_CLIC_CTRL_BASE + (i) * 4)
/* CLIC_INT_CTL : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
/*description: .*/
#define CLIC_INT_CTL 0x000000FF
#define CLIC_INT_CTL_M ((CLIC_INT_CTL_V)<<(CLIC_INT_CTL_S))
#define CLIC_INT_CTL_V 0xFF
#define CLIC_INT_CTL_S 24
/* CLIC_INT_ATTR_MODE : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
/*description: .*/
#define CLIC_INT_ATTR_MODE 0x00000003
#define CLIC_INT_ATTR_MODE_M ((CLIC_INT_ATTR_MODE_V)<<(CLIC_INT_ATTR_MODE_S))
#define CLIC_INT_ATTR_MODE_V 0x3
#define CLIC_INT_ATTR_MODE_S 22
/* CLIC_INT_ATTR_TRIG : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
/*description: .*/
#define CLIC_INT_ATTR_TRIG 0x00000003
#define CLIC_INT_ATTR_TRIG_M ((CLIC_INT_ATTR_TRIG_V)<<(CLIC_INT_ATTR_TRIG_S))
#define CLIC_INT_ATTR_TRIG_V 0x3
#define CLIC_INT_ATTR_TRIG_S 17
/* CLIC_INT_ATTR_SHV : R/W ;bitpos:[16] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_ATTR_SHV (BIT(16))
#define CLIC_INT_ATTR_SHV_M (BIT(16))
#define CLIC_INT_ATTR_SHV_V 0x1
#define CLIC_INT_ATTR_SHV_S 16
/* CLIC_INT_IE : R/W ;bitpos:[8] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_IE (BIT(8))
#define CLIC_INT_IE_M (BIT(8))
#define CLIC_INT_IE_V 0x1
#define CLIC_INT_IE_S 8
/* CLIC_INT_IP : R/W ;bitpos:[0] ;default: 1'd0 ; */
/*description: .*/
#define CLIC_INT_IP (BIT(0))
#define CLIC_INT_IP_M (BIT(0))
#define CLIC_INT_IP_V 0x1
#define CLIC_INT_IP_S 0
#ifdef __cplusplus
}
#endif

485
components/soc/esp32c5/include/soc/clk_tree_defs.h Normal file
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@@ -0,0 +1,485 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/*
************************* ESP32C5 Root Clock Source ****************************
* 1) Internal 17.5MHz RC Oscillator: RC_FAST (may also referred as FOSC in TRM and reg. description)
*
* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
*
* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
*
* 2) External 40MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
*
* 4) Internal 32kHz RC Oscillator: RC32K
*
* The exact frequency of this clock can be computed in runtime through calibration.
*
* 5) External 32kHz Crystal Clock (optional): XTAL32K
*
* The clock source for this XTAL32K_CLK should be a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
* pins.
*
* XTAL32K_CLK can also be calibrated to get its exact frequency.
*
* 6) External Slow Clock (optional): OSC_SLOW
*
* A slow clock signal generated by an external circuit can be connected to GPIO0 to be the clock source for the
* RTC_SLOW_CLK.
*
* OSC_SLOW_CLK can also be calibrated to get its exact frequency.
*/
// TODO: [ESP32C5] IDF-8642 (inherit from C6)
/* With the default value of FOSC_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000 /*!< Approximate RC_FAST_CLK frequency in Hz */
#define SOC_CLK_RC_SLOW_FREQ_APPROX 136000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
#define SOC_CLK_OSC_SLOW_FREQ_APPROX 32768 /*!< Approximate OSC_SLOW_CLK (external slow clock) frequency in Hz */
// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
// {loc}: EXT, INT
// {type}: XTAL, RC
// [attr] - optional: [frequency], FAST, SLOW
/**
* @brief Root clock
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal */
SOC_ROOT_CLK_INT_RC32K, /*!< Internal 32kHz RC oscillator */
SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */
} soc_root_clk_t;
/**
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
/**
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_OSC_SLOW = 3, /*!< Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
} soc_rtc_slow_clk_src_t;
/**
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
} soc_rtc_fast_clk_src_t;
// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
// {[upstream]clock_name}: XTAL, (BB)PLL, etc.
// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
/**
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
*
* @note enum starts from 1, to save 0 for special purpose
*/
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
// For CPU domain
SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
// For RTC domain
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */
// For LP peripherals
SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
} soc_module_clk_t;
//////////////////////////////////////////////////SYSTIMER//////////////////////////////////////////////////////////////
/**
* @brief Type of SYSTIMER clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6)
SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
} soc_periph_systimer_clk_src_t;
//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of GPTimer
*
* The following code can be used to iterate all possible clocks:
* @code{c}
* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
* // Test GPTimer with the clock `clk`
* }
* @endcode
*/
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of GPTimer clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of RMT
*/
#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of RMT clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6)
RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_rmt_clk_src_t;
/**
* @brief Type of RMT clock source, reserved for the legacy RMT driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8726 (inherit from C6)
RMT_BASECLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock is PLL_F80M */
RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Temperature Sensor
*/
#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of Temp Sensor clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8727 (inherit from C6)
TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8722 (inherit from C6)
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
} soc_periph_uart_clk_src_legacy_t;
/**
* @brief Type of LP_UART clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6)
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Carrier
*/
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2S
*/
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
/**
* @brief I2S clock source enum
*/
typedef enum { // TODO: [ESP32C5] IDF-8713 (inherit from C6)
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
} soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I2C
*/
#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of I2C clock source.
*/
typedef enum { // TODO: [ESP32C5] IDF-8694, IDF-8696 (inherit from C6)
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
///////////////////////////////////////////////LP_I2C///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LP_I2C
*/
#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
/**
* @brief Type of LP_I2C clock source.
*/
typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6)
LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */
LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */
LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */
} soc_periph_lp_i2c_clk_src_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SPI
*/
#define SOC_SPI_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of SPI clock source.
*/
typedef enum { // TODO: [ESP32C5] IDF-8698, IDF-8699 (inherit from C6)
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_80M as SPI source clock */
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as SPI source clock */
} soc_periph_spi_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of SDM
*/
#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Sigma Delta Modulator clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8687 (inherit from C6)
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Glitch Filter
*/
#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Glitch filter clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8718 (inherit from C6)
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of TWAI
*/
#define SOC_TWAI_CLKS {SOC_MOD_CLK_XTAL}
/**
* @brief TWAI clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6)
TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_twai_clk_src_t;
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of ADC digital controller
*/
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief ADC digital controller clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6)
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MWDT
*/
#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief MWDT clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8650 (inherit from C6)
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */
MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select PLL fixed 80 MHz as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LEDC
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8684 (inherit from C6)
LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////PARLIO////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PARLIO
*/
#define SOC_PARLIO_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F240M}
/**
* @brief PARLIO clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8685, IDF-8686 (inherit from C6)
PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PARLIO_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the default clock choice */
} soc_periph_parlio_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum { // TODO: [ESP32C5] IDF-8642 (inherit from C6)
CLKOUT_SIG_PLL = 1, /*!< PLL_CLK is the output of crystal oscillator frequency multiplier */
CLKOUT_SIG_XTAL = 5, /*!< Main crystal oscillator clock */
CLKOUT_SIG_PLL_F80M = 13, /*!< From PLL, usually be 80MHz */
CLKOUT_SIG_CPU = 16, /*!< CPU clock */
CLKOUT_SIG_AHB = 17, /*!< AHB clock */
CLKOUT_SIG_APB = 18, /*!< APB clock */
CLKOUT_SIG_XTAL32K = 21, /*!< External 32kHz crystal clock */
CLKOUT_SIG_EXT32K = 22, /*!< External slow clock input through XTAL_32K_P */
CLKOUT_SIG_RC_FAST = 23, /*!< RC fast clock, about 17.5MHz */
CLKOUT_SIG_RC_32K = 24, /*!< Internal slow RC oscillator */
CLKOUT_SIG_RC_SLOW = 25, /*!< RC slow clock, depends on the RTC_CLK_SRC configuration */
CLKOUT_SIG_INVALID = 0xFF,
} soc_clkout_sig_id_t;
#ifdef __cplusplus
}
#endif

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components/soc/esp32c5/include/soc/dport_access.h Normal file
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
* @brief Read a sequence of DPORT registers to the buffer.
*
* @param[out] buff_out Contains the read data.
* @param[in] address Initial address for reading registers.
* @param[in] num_words The number of words.
*/
void esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address, uint32_t num_words);
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
// Write value to DPORT register (does not require protecting)
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
//get bit or get bits from register
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
//set bit or set bits to register
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
//clear bit or clear bits of register
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
//set bits of register controlled by mask
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
//get field from register, uses field _S & _V to determine mask
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
//set field to register, used when _f is not left shifted by _f##_S
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
//get field value from a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
//write value to register
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
//clear bits of register controlled by mask
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
//set bits of register controlled by mask
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
//get bits of register controlled by mask
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
//get bits of register controlled by highest bit and lowest bit
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
//set bits of register controlled by mask and shift
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
//get field of register
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
//}}
#ifdef __cplusplus
}
#endif

3
components/soc/esp32c5/include/soc/efuse_struct.h
View File

@@ -431,11 +431,12 @@ typedef union {
*/
typedef union {
struct {
// TODO: [ESP32C5] IDF-8674 (inherit from C6) seems an error in csv, need to check
uint32_t reserved_0:24;
/** reserved_0 : RO; bitpos: [31:24]; default: 0;
* Reserved.
*/
uint32_t reserved_0:8;
uint32_t reserved_24:8;
};
uint32_t val;
} efuse_rd_repeat_data4_reg_t;

20
components/soc/esp32c5/include/soc/gpio_pins.h Normal file
View File

@@ -0,0 +1,20 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
// TODO: [ESP32C5] IDF-8717 (inherit from C6)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x3F)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3E)
#ifdef __cplusplus
}
#endif

177
components/soc/esp32c5/include/soc/gpio_sig_map.h Normal file
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@@ -0,0 +1,177 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define EXT_ADC_START_IDX 0
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2
#define LEDC_LS_SIG_OUT3_IDX 3
#define LEDC_LS_SIG_OUT4_IDX 4
#define LEDC_LS_SIG_OUT5_IDX 5
#define U0RXD_IN_IDX 6
#define U0TXD_OUT_IDX 6
#define U0CTS_IN_IDX 7
#define U0RTS_OUT_IDX 7
#define U0DSR_IN_IDX 8
#define U0DTR_OUT_IDX 8
#define U1RXD_IN_IDX 9
#define U1TXD_OUT_IDX 9
#define U1CTS_IN_IDX 10
#define U1RTS_OUT_IDX 10
#define U1DSR_IN_IDX 11
#define U1DTR_OUT_IDX 11
#define I2S_MCLK_IN_IDX 12
#define I2S_MCLK_OUT_IDX 12
#define I2SO_BCK_IN_IDX 13
#define I2SO_BCK_OUT_IDX 13
#define I2SO_WS_IN_IDX 14
#define I2SO_WS_OUT_IDX 14
#define I2SI_SD_IN_IDX 15
#define I2SO_SD_OUT_IDX 15
#define I2SI_BCK_IN_IDX 16
#define I2SI_BCK_OUT_IDX 16
#define I2SI_WS_IN_IDX 17
#define I2SI_WS_OUT_IDX 17
#define I2SO_SD1_OUT_IDX 18
#define USB_JTAG_TDO_BRIDGE_IDX 19
#define USB_JTAG_TRST_IDX 19
#define USB_OTG_32K_IN_IDX 21
#define CPU_GPIO_IN0_IDX 28
#define CPU_GPIO_OUT0_IDX 28
#define CPU_GPIO_IN1_IDX 29
#define CPU_GPIO_OUT1_IDX 29
#define CPU_GPIO_IN2_IDX 30
#define CPU_GPIO_OUT2_IDX 30
#define CPU_GPIO_IN3_IDX 31
#define CPU_GPIO_OUT3_IDX 31
#define CPU_GPIO_IN4_IDX 32
#define CPU_GPIO_OUT4_IDX 32
#define CPU_GPIO_IN5_IDX 33
#define CPU_GPIO_OUT5_IDX 33
#define CPU_GPIO_IN6_IDX 34
#define CPU_GPIO_OUT6_IDX 34
#define CPU_GPIO_IN7_IDX 35
#define CPU_GPIO_OUT7_IDX 35
#define I2CEXT0_SCL_IN_IDX 45
#define I2CEXT0_SCL_OUT_IDX 45
#define I2CEXT0_SDA_IN_IDX 46
#define I2CEXT0_SDA_OUT_IDX 46
#define PARL_RX_DATA0_IDX 47
#define PARL_TX_DATA0_IDX 47
#define PARL_RX_DATA1_IDX 48
#define PARL_TX_DATA1_IDX 48
#define PARL_RX_DATA2_IDX 49
#define PARL_TX_DATA2_IDX 49
#define PARL_RX_DATA3_IDX 50
#define PARL_TX_DATA3_IDX 50
#define PARL_RX_DATA4_IDX 51
#define PARL_TX_DATA4_IDX 51
#define PARL_RX_DATA5_IDX 52
#define PARL_TX_DATA5_IDX 52
#define PARL_RX_DATA6_IDX 53
#define PARL_TX_DATA6_IDX 53
#define PARL_RX_DATA7_IDX 54
#define PARL_TX_DATA7_IDX 54
#define SDIO_TOHOST_INT_OUT_IDX 62
#define FSPICLK_IN_IDX 63
#define FSPICLK_OUT_MUX_IDX 63
#define FSPIQ_IN_IDX 64
#define FSPIQ_OUT_IDX 64
#define FSPID_IN_IDX 65
#define FSPID_OUT_IDX 65
#define FSPIHD_IN_IDX 66
#define FSPIHD_OUT_IDX 66
#define FSPIWP_IN_IDX 67
#define FSPIWP_OUT_IDX 67
#define FSPICS0_IN_IDX 68
#define FSPICS0_OUT_IDX 68
#define PARL_RX_CLK_IN_IDX 69
#define PARL_RX_CLK_OUT_IDX 69
#define PARL_TX_CLK_IN_IDX 70
#define PARL_TX_CLK_OUT_IDX 70
#define RMT_SIG_IN0_IDX 71
#define RMT_SIG_OUT0_IDX 71
#define RMT_SIG_IN1_IDX 72
#define RMT_SIG_OUT1_IDX 72
#define TWAI0_RX_IDX 73
#define TWAI0_TX_IDX 73
#define TWAI0_BUS_OFF_ON_IDX 74
#define TWAI0_CLKOUT_IDX 75
#define TWAI0_STANDBY_IDX 76
#define TWAI1_RX_IDX 77
#define TWAI1_TX_IDX 77
#define TWAI1_BUS_OFF_ON_IDX 78
#define TWAI1_CLKOUT_IDX 79
#define TWAI1_STANDBY_IDX 80
#define PCNT_RST_IN0_IDX 83
#define GPIO_SD0_OUT_IDX 83
#define PCNT_RST_IN1_IDX 84
#define GPIO_SD1_OUT_IDX 84
#define PCNT_RST_IN2_IDX 85
#define GPIO_SD2_OUT_IDX 85
#define PCNT_RST_IN3_IDX 86
#define GPIO_SD3_OUT_IDX 86
#define PWM0_SYNC0_IN_IDX 87
#define PWM0_OUT0A_IDX 87
#define PWM0_SYNC1_IN_IDX 88
#define PWM0_OUT0B_IDX 88
#define PWM0_SYNC2_IN_IDX 89
#define PWM0_OUT1A_IDX 89
#define PWM0_F0_IN_IDX 90
#define PWM0_OUT1B_IDX 90
#define PWM0_F1_IN_IDX 91
#define PWM0_OUT2A_IDX 91
#define PWM0_F2_IN_IDX 92
#define PWM0_OUT2B_IDX 92
#define PWM0_CAP0_IN_IDX 93
#define PWM0_CAP1_IN_IDX 94
#define PWM0_CAP2_IN_IDX 95
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define PCNT_SIG_CH0_IN0_IDX 101
#define FSPICS1_OUT_IDX 101
#define PCNT_SIG_CH1_IN0_IDX 102
#define FSPICS2_OUT_IDX 102
#define PCNT_CTRL_CH0_IN0_IDX 103
#define FSPICS3_OUT_IDX 103
#define PCNT_CTRL_CH1_IN0_IDX 104
#define FSPICS4_OUT_IDX 104
#define PCNT_SIG_CH0_IN1_IDX 105
#define FSPICS5_OUT_IDX 105
#define PCNT_SIG_CH1_IN1_IDX 106
#define PCNT_CTRL_CH0_IN1_IDX 107
#define PCNT_CTRL_CH1_IN1_IDX 108
#define PCNT_SIG_CH0_IN2_IDX 109
#define PCNT_SIG_CH1_IN2_IDX 110
#define PCNT_CTRL_CH0_IN2_IDX 111
#define PCNT_CTRL_CH1_IN2_IDX 112
#define PCNT_SIG_CH0_IN3_IDX 113
#define PCNT_SIG_CH1_IN3_IDX 114
#define SPICLK_OUT_MUX_IDX 114
#define PCNT_CTRL_CH0_IN3_IDX 115
#define SPICS0_OUT_IDX 115
#define PCNT_CTRL_CH1_IN3_IDX 116
#define SPICS1_OUT_IDX 116
#define SPIQ_IN_IDX 121
#define SPIQ_OUT_IDX 121
#define SPID_IN_IDX 122
#define SPID_OUT_IDX 122
#define SPIHD_IN_IDX 123
#define SPIHD_OUT_IDX 123
#define SPIWP_IN_IDX 124
#define SPIWP_OUT_IDX 124
#define CLK_OUT_OUT1_IDX 125
#define CLK_OUT_OUT2_IDX 126
#define CLK_OUT_OUT3_IDX 127
#define GPIO_MAP_DATE_IDX 0x2301100

2
components/soc/esp32c5/include/soc/interrupt_matrix_reg.h
View File

@@ -5,8 +5,8 @@
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

22
components/soc/esp32c5/include/soc/interrupt_reg.h Normal file
View File

@@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/reg_base.h"
#include "soc/interrupt_matrix_reg.h"
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"
/**
* ESP32C5 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
*
* The memory map for interrupt registers is on a per-core basis, CLIC_INT_THRESH_REG points to
* the current core interrupt register, whereas CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF points
* to the other core registers, regardless of the core we are currently running on.
*/
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG

106
components/soc/esp32c5/include/soc/interrupts.h Normal file
View File

@@ -0,0 +1,106 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
// TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from C6)
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_ZB_MAC_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_UART_INTR_SOURCE,
ETS_LP_I2C_INTR_SOURCE,
ETS_LP_WDT_INTR_SOURCE,
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
ETS_LP_APM_M0_INTR_SOURCE,
ETS_LP_APM_M1_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
ETS_HP_APM_M0_INTR_SOURCE,
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_TWAI0_INTR_SOURCE, /**< interrupt of twai0, level*/
ETS_TWAI1_INTR_SOURCE, /**< interrupt of twai1, level*/
ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
ETS_APB_ADC_INTR_SOURCE = 60, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_INTR_SOURCE,
ETS_SLC0_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/
ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/
ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/
ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/
ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/
ETS_GSPI2_INTR_SOURCE,
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
#ifdef __cplusplus
}
#endif

1
components/soc/esp32c5/include/soc/lp_timer_struct.h
View File

@@ -311,6 +311,7 @@ typedef struct lp_timer_dev_t {
volatile lp_timer_target_reg_t target[2];
volatile lp_timer_update_reg_t update;
volatile lp_timer_counter_reg_t counter[2];
volatile lp_timer_main_overflow_reg_t main_overflow;
volatile lp_timer_int_raw_reg_t int_raw;
volatile lp_timer_int_st_reg_t int_st;
volatile lp_timer_int_ena_reg_t int_ena;

4
components/soc/esp32c5/include/soc/pcr_struct.h
View File

@@ -1795,11 +1795,11 @@ typedef union {
*/
typedef union {
struct {
/** 32k_sel : R/W; bitpos: [1:0]; default: 0;
/** clk_32k_sel : R/W; bitpos: [1:0]; default: 0;
* This field indicates which one 32KHz clock will be used by timergroup. 0:
* OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
*/
uint32_t 32k_sel:2;
uint32_t clk_32k_sel:2;
uint32_t reserved_2:30;
};
uint32_t val;

87
components/soc/esp32c5/include/soc/periph_defs.h Normal file
View File

@@ -0,0 +1,87 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/interrupts.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: [ESP32C5-PERIPH] (inherit from C6)
typedef enum {
/* HP peripherals */
PERIPH_LEDC_MODULE = 0,
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE, // USB Serial Jtag
PERIPH_I2C0_MODULE,
PERIPH_I2C1_MODULE,
PERIPH_I2S1_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,
PERIPH_UHCI0_MODULE,
PERIPH_RMT_MODULE,
PERIPH_PCNT_MODULE,
PERIPH_MSPI0_MODULE, //SPI0
PERIPH_MSPI1_MODULE, //SPI1
PERIPH_GPSPI2_MODULE, //SPI2
PERIPH_TWAI0_MODULE,
PERIPH_TWAI1_MODULE,
PERIPH_RNG_MODULE,
PERIPH_RSA_MODULE,
PERIPH_AES_MODULE,
PERIPH_SHA_MODULE,
PERIPH_ECC_MODULE,
PERIPH_HMAC_MODULE,
PERIPH_DS_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_MCPWM0_MODULE,
PERIPH_ETM_MODULE,
PERIPH_PARLIO_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,
PERIPH_TEMPSENSOR_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
PERIPH_INT_MATRIX_MODULE,
PERIPH_PVT_MONITOR_MODULE,
PERIPH_BITSCRAMBLER_MODULE,
PERIPH_KEY_MANAGE_MODULE,
PERIPH_ECDSA_MODULE,
PERIPH_MEM_MONITOR_MODULE,
PERIPH_TEE_MODULE,
PERIPH_HP_APM_MODULE,
/* LP peripherals */
PERIPH_LP_I2C0_MODULE,
PERIPH_LP_UART0_MODULE,
PERIPH_LP_TEE_MODULE,
PERIPH_LP_APM_MODULE,
PERIPH_LP_ANA_PERI_MODULE,
PERIPH_LP_PERI_MODULE,
PERIPH_HUK_MODULE,
PERIPH_OTP_DEBUG_MODULE,
/* Peripherals clock managed by the modem_clock driver must be listed last in the enumeration */
PERIPH_WIFI_MODULE,
PERIPH_BT_MODULE,
PERIPH_COEX_MODULE,
PERIPH_PHY_MODULE,
PERIPH_ANA_I2C_MASTER_MODULE,
PERIPH_MODEM_ETM_MODULE,
PERIPH_MODEM_ADC_COMMON_FE_MODULE,
PERIPH_MODULE_MAX
/* !!! Don't append soc modules here !!! */
} periph_module_t;
#define PERIPH_MODEM_MODULE_MIN PERIPH_WIFI_MODULE
#define PERIPH_MODEM_MODULE_MAX PERIPH_MODEM_ADC_COMMON_FE_MODULE
#define PERIPH_MODEM_MODULE_NUM (PERIPH_MODEM_MODULE_MAX - PERIPH_MODEM_MODULE_MIN + 1)
#define IS_MODEM_MODULE(periph) ((periph>=PERIPH_MODEM_MODULE_MIN) && (periph<=PERIPH_MODEM_MODULE_MAX))
#ifdef __cplusplus
}
#endif

5
components/soc/esp32c5/include/soc/reg_base.h
View File

@@ -13,7 +13,7 @@
#define DR_REG_SPIMEM0_BASE 0x60002000
#define DR_REG_SPIMEM1_BASE 0x60003000
#define DR_REG_I2C0_BASE 0x60004000
#define DR_REG_UHCI0_BASE 0x60005000
#define DR_REG_UHCI_BASE 0x60005000
#define DR_REG_RMT_BASE 0x60006000
#define DR_REG_LEDC_BASE 0x60007000
#define DR_REG_TIMERG0_BASE 0x60008000
@@ -24,7 +24,8 @@
#define DR_REG_TWAI1_BASE 0x6000D000
#define DR_REG_APB_SARADC_BASE 0x6000E000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
#define DR_REG_INTMTX_BASE 0x60010000
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_MATRIX_BASE
#define DR_REG_I2C1_BASE 0x60011000
#define DR_REG_PCNT_BASE 0x60012000
#define DR_REG_SOC_ETM_BASE 0x60013000

55
components/soc/esp32c5/include/soc/reset_reasons.h Normal file
View File

@@ -0,0 +1,55 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
//+-----------------------------------------------Terminology---------------------------------------------+
//| |
//| CPU Reset: Reset CPU core only, once reset done, CPU will execute from reset vector |
//| |
//| Core Reset: Reset the whole digital system except RTC sub-system |
//| |
//| System Reset: Reset the whole digital system, including RTC sub-system |
//| |
//| Chip Reset: Reset the whole chip, including the analog part |
//| |
//+-------------------------------------------------------------------------------------------------------+
#ifdef __cplusplus
extern "C" {
#endif
// TODO: [ESP32C5] IDF-8660 (inherit from P4)
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup if 0x5/0x6 is deepsleep wakeup TODO IDF-7529
RESET_REASON_SYS_PMU_PWR_DOWN = 0x05, // PMU HP power down system reset
RESET_REASON_CPU_PMU_PWR_DOWN = 0x06, // PMU HP power down CPU reset
RESET_REASON_SYS_HP_WDT = 0x07, // HP WDT resets system
RESET_REASON_SYS_LP_WDT = 0x09, // LP WDT resets system
RESET_REASON_CORE_HP_WDT = 0x0B, // HP WDT resets digital core
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0
RESET_REASON_CORE_LP_WDT = 0x0D, // LP WDT resets digital core
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_CHIP_LP_WDT = 0x10, // LP WDT resets chip
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core
RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core
RESET_REASON_CPU_JTAG = 0x18, // Glitch on power resets the digital core
} soc_reset_reason_t;
#ifdef __cplusplus
}
#endif

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// TODO: [ESP32C5] IDF-8719 (inherit from C6)
//RTC GPIO channels
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
#define RTCIO_CHANNEL_0_GPIO_NUM 0
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
#define RTCIO_CHANNEL_1_GPIO_NUM 1
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
#define RTCIO_CHANNEL_2_GPIO_NUM 2
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
#define RTCIO_CHANNEL_3_GPIO_NUM 3
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
#define RTCIO_CHANNEL_4_GPIO_NUM 4
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
#define RTCIO_CHANNEL_5_GPIO_NUM 5
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
#define RTCIO_CHANNEL_6_GPIO_NUM 6
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
#define RTCIO_CHANNEL_7_GPIO_NUM 7

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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifndef __ASSEMBLER__
#include <stdint.h>
#include "esp_assert.h"
#endif
#include "esp_bit_defs.h"
#include "reg_base.h"
#define PRO_CPU_NUM (0)
/**
* @brief Reg base address for multi-instance peripherals
* @note common multi-instance peripherals includes
* I2C, I2S, UART, UHCI, SPI, SPIMEM, MCPWM, TWAI, TIMER_GROUP
* please check `reg_base.h` and the corresponding `xxx_reg.h` whether the base addresses are match
*/
#define REG_I2C_BASE(i) ((i) == 0 ? DR_REG_I2C0_BASE : DR_REG_I2C1_BASE) // two I2C on C5
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_TWAI_BASE(i) ((i) == 0 ? DR_REG_TWAI0_BASE : DR_REG_TWAI1_BASE) // TWAI0 and TWAI1
#define REG_UART_BASE(i) (DR_REG_UART0_BASE + (i) * 0x1000) // UART0 and UART1
//Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#ifndef __ASSEMBLER__
//write value to register
#define REG_WRITE(_r, _v) do { \
(*(volatile uint32_t *)(_r)) = (_v); \
} while(0)
//read value from register
#define REG_READ(_r) ({ \
(*(volatile uint32_t *)(_r)); \
})
//get bit or get bits from register
#define REG_GET_BIT(_r, _b) ({ \
(*(volatile uint32_t*)(_r) & (_b)); \
})
//set bit or set bits to register
#define REG_SET_BIT(_r, _b) do { \
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \
} while(0)
//clear bit or clear bits of register
#define REG_CLR_BIT(_r, _b) do { \
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \
} while(0)
//set bits of register controlled by mask
#define REG_SET_BITS(_r, _b, _m) do { \
*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \
} while(0)
//get field from register, uses field _S & _V to determine mask
#define REG_GET_FIELD(_r, _f) ({ \
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
})
//set field of a register from variable, uses field _S & _V to determine mask
#define REG_SET_FIELD(_r, _f, _v) do { \
REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \
} while(0)
//get field value from a variable, used when _f is not left shifted by _f##_S
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
//get field value from a variable, used when _f is left shifted by _f##_S
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
//set field value to a variable, used when _f is not left shifted by _f##_S
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
//set field value to a variable, used when _f is left shifted by _f##_S
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
//generate a value from a field value, used when _f is not left shifted by _f##_S
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
//generate a value from a field value, used when _f is left shifted by _f##_S
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
//read value from register
#define READ_PERI_REG(addr) ({ \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
})
//write value to register
#define WRITE_PERI_REG(addr, val) do { \
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
} while(0)
//clear bits of register controlled by mask
#define CLEAR_PERI_REG_MASK(reg, mask) do { \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
} while(0)
//set bits of register controlled by mask
#define SET_PERI_REG_MASK(reg, mask) do { \
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
} while(0)
//get bits of register controlled by mask
#define GET_PERI_REG_MASK(reg, mask) ({ \
(READ_PERI_REG(reg) & (mask)); \
})
//get bits of register controlled by highest bit and lowest bit
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
})
//set bits of register controlled by mask and shift
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \
WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \
} while(0)
//get field of register
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
((READ_PERI_REG(reg)>>(shift))&(mask)); \
})
#endif /* !__ASSEMBLER__ */
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 )
#define XTAL_CLK_FREQ (40*1000000)
#define GPIO_MATRIX_DELAY_NS 0
//}}
/* Overall memory map */
/* Note: We should not use MACROs similar in cache_memory.h
* those are defined during run-time. But the MACROs here
* should be defined statically!
*/
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8))
#define SOC_DROM_LOW SOC_IROM_LOW
#define SOC_DROM_HIGH SOC_IROM_HIGH
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40050000
#define SOC_DROM_MASK_LOW 0x40000000
#define SOC_DROM_MASK_HIGH 0x40050000
#define SOC_IRAM_LOW 0x40800000
#define SOC_IRAM_HIGH 0x40880000
#define SOC_DRAM_LOW 0x40800000
#define SOC_DRAM_HIGH 0x40880000
#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C5 only has 16k LP memory
#define SOC_RTC_IRAM_HIGH 0x50004000
#define SOC_RTC_DRAM_LOW 0x50000000
#define SOC_RTC_DRAM_HIGH 0x50004000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50004000
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40800000
#define SOC_DIRAM_IRAM_HIGH 0x40880000
#define SOC_DIRAM_DRAM_LOW 0x40800000
#define SOC_DIRAM_DRAM_HIGH 0x40880000
#define MAP_DRAM_TO_IRAM(addr) (addr)
#define MAP_IRAM_TO_DRAM(addr) (addr)
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
#define SOC_DMA_LOW 0x40800000
#define SOC_DMA_HIGH 0x40880000
// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000
#define SOC_BYTE_ACCESSIBLE_HIGH 0x40880000
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
#define SOC_MEM_INTERNAL_LOW 0x40800000
#define SOC_MEM_INTERNAL_HIGH 0x40880000
#define SOC_MEM_INTERNAL_LOW1 0x40800000
#define SOC_MEM_INTERNAL_HIGH1 0x40880000
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
// Region of address space that holds peripherals
#define SOC_PERIPHERAL_LOW 0x60000000
#define SOC_PERIPHERAL_HIGH 0x60100000
// Debug region, not used by software
#define SOC_DEBUG_LOW 0x20000000
#define SOC_DEBUG_HIGH 0x28000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4087e610
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
//CPU0 Interrupt numbers used in components/riscv/vectors.S. Change it's logic if modifying
#define ETS_T1_WDT_INUM 24
#define ETS_CACHEERR_INUM 25
#define ETS_MEMPROT_ERR_INUM 26
#define ETS_ASSIST_DEBUG_INUM 27 // Note: this interrupt can be combined with others (e.g., CACHEERR), as we can identify its trigger is activated
//CPU0 Max valid interrupt number
#define ETS_MAX_INUM 31
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
#define ETS_SPI2_INUM 1
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
#define ETS_GPIO_INUM 4
//Other interrupt number should be managed by the user
//Invalid interrupt for number interrupt matrix
#define ETS_INVALID_INUM 0
//Interrupt medium level, used for INT WDT for example
#define SOC_INTERRUPT_LEVEL_MEDIUM 4
// Interrupt number for the Interrupt watchdog
#define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM)

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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* These defines are parsed and imported as kconfig variables via the script
* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
*
* If this file is changed the script will automatically run the script
* and generate the kconfig variables as part of the pre-commit hooks.
*
* It can also be run manually. For more information, see `${IDF_PATH}/tools/gen_soc_caps_kconfig/README.md`
*/
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1
// #define SOC_UART_SUPPORTED 1
// #define SOC_GDMA_SUPPORTED 1
// #define SOC_AHB_GDMA_SUPPORTED 1
// #define SOC_GPTIMER_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1
// #define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1
// #define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1
// #define SOC_BT_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1
// #define SOC_TEMP_SENSOR_SUPPORTED 1
// #define SOC_WIFI_SUPPORTED 1
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
// #define SOC_ULP_SUPPORTED 1
// #define SOC_LP_CORE_SUPPORTED 1
// #define SOC_EFUSE_KEY_PURPOSE_FIELD 1
// #define SOC_EFUSE_SUPPORTED 1
// #define SOC_RTC_FAST_MEM_SUPPORTED 1
// #define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1
// #define SOC_RMT_SUPPORTED 1
// #define SOC_SDM_SUPPORTED 1
// #define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1
// #define SOC_I2C_SUPPORTED 1
// #define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_SUPPORT_COEXISTENCE 1
// #define SOC_AES_SUPPORTED 1
// #define SOC_MPI_SUPPORTED 1
// #define SOC_SHA_SUPPORTED 1
// #define SOC_HMAC_SUPPORTED 1
// #define SOC_DIG_SIGN_SUPPORTED 1
// #define SOC_ECC_SUPPORTED 1
// #define SOC_FLASH_ENC_SUPPORTED 1
// #define SOC_SECURE_BOOT_SUPPORTED 1
// #define SOC_SDIO_SLAVE_SUPPORTED 1
// #define SOC_BOD_SUPPORTED 1
// #define SOC_APM_SUPPORTED 1
// #define SOC_PMU_SUPPORTED 1
// #define SOC_PAU_SUPPORTED 1
// #define SOC_LP_TIMER_SUPPORTED 1
// #define SOC_LP_AON_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_LP_I2C_SUPPORTED 1
// #define SOC_ULP_LP_UART_SUPPORTED 1
// #define SOC_CLK_TREE_SUPPORTED 1
// #define SOC_ASSIST_DEBUG_SUPPORTED 1
// #define SOC_WDT_SUPPORTED 1
// #define SOC_SPI_FLASH_SUPPORTED 1
// #define SOC_BITSCRAMBLER_SUPPORTED 1
// #define SOC_ECDSA_SUPPORTED 1
// #define SOC_KEY_MANAGER_SUPPORTED 1
#define SOC_INT_HW_NESTED_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/
// #define SOC_XTAL_SUPPORT_40M 1
/*-------------------------- AES CAPS -----------------------------------------*/
// #define SOC_AES_SUPPORT_DMA (1)
/* Has a centralized DMA, which is shared with all peripherals */
// #define SOC_AES_GDMA (1)
// #define SOC_AES_SUPPORT_AES_128 (1)
// #define SOC_AES_SUPPORT_AES_256 (1)
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
// #define SOC_ADC_DIG_CTRL_SUPPORTED 1
// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
// #define SOC_ADC_MONITOR_SUPPORTED 1
// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
// #define SOC_ADC_DMA_SUPPORTED 1
// #define SOC_ADC_PERIPH_NUM (1U)
// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7)
// #define SOC_ADC_MAX_CHANNEL_NUM (7)
// #define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
// #define SOC_ADC_DIGI_MAX_BITWIDTH (12)
// #define SOC_ADC_DIGI_MIN_BITWIDTH (12)
// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
// #define SOC_ADC_DIGI_MONITOR_NUM (2)
// #define SOC_ADC_DIGI_RESULT_BYTES (4)
// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
// #define SOC_ADC_RTC_MIN_BITWIDTH (12)
// #define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
// #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< Interrupt */
// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
/*!< ADC power control is shared by PWDET */
// #define SOC_ADC_SHARED_POWER 1
// ESP32C5-TODO: Copy from esp32C5, need check
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
// #define SOC_APB_BACKUP_DMA (0)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
// #define SOC_BROWNOUT_RESET_SUPPORTED 1
/*-------------------------- CACHE CAPS --------------------------------------*/
// #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data
// #define SOC_CACHE_FREEZE_SUPPORTED 1
/*-------------------------- CPU CAPS ----------------------------------------*/
#define SOC_CPU_CORES_NUM (1U)
// #define SOC_CPU_INTR_NUM 32
// #define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_INT_CLIC_SUPPORTED 1
// #define SOC_CPU_BREAKPOINTS_NUM 4
// #define SOC_CPU_WATCHPOINTS_NUM 4
// #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes
// #define SOC_CPU_HAS_PMA 1
// #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/
/** The maximum length of a Digital Signature in bits. */
// #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072)
/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */
// #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16)
/** Maximum wait time for DS parameter decryption key. If overdue, then key error.
See TRM DS chapter for more details */
// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- GDMA CAPS -------------------------------------*/
// #define SOC_AHB_GDMA_VERSION 1U
// #define SOC_GDMA_NUM_GROUPS_MAX 1U
// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
/*-------------------------- ETM CAPS --------------------------------------*/
// #define SOC_ETM_GROUPS 1U // Number of ETM groups
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C5 has 1 GPIO peripheral
// #define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 31
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8
// Target has the full LP IO subsystem
// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// #define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
// #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
// #define SOC_GPIO_IN_RANGE_MAX 30
// #define SOC_GPIO_OUT_RANGE_MAX 30
// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
// #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
// Support to force hold all IOs
// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
// #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)
// The Clock Out singnal is route to the pin by GPIO matrix
// #define SOC_GPIO_CLOCKOUT_BY_GPIO_MATRIX (1)
/*-------------------------- RTCIO CAPS --------------------------------------*/
// #define SOC_RTCIO_PIN_COUNT 8
// #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature,
// * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.)
// * when the pins are switched to RTC function.
// */
// #define SOC_RTCIO_HOLD_SUPPORTED 1
// #define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C5 has 1 I2C
// #define SOC_I2C_NUM (1U)
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// #define SOC_I2C_SUPPORT_SLAVE (1)
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
// #define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1)
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
/*-------------------------- LP_I2C CAPS -------------------------------------*/
// ESP32-C5 has 1 LP_I2C
// #define SOC_LP_I2C_NUM (1U)
// #define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
/*-------------------------- I2S CAPS ----------------------------------------*/
// #define SOC_I2S_NUM (1U)
// #define SOC_I2S_HW_VERSION_2 (1)
// #define SOC_I2S_SUPPORTS_XTAL (1)
// #define SOC_I2S_SUPPORTS_PLL_F160M (1)
// #define SOC_I2S_SUPPORTS_PCM (1)
// #define SOC_I2S_SUPPORTS_PDM (1)
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
// #define SOC_I2S_SUPPORTS_TDM (1)
/*-------------------------- LEDC CAPS ---------------------------------------*/
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
// #define SOC_LEDC_CHANNEL_NUM (6)
// #define SOC_LEDC_TIMER_BIT_WIDTH (20)
// #define SOC_LEDC_SUPPORT_FADE_STOP (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
/*-------------------------- MMU CAPS ----------------------------------------*/
// #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
// #define SOC_MMU_PERIPH_NUM (1U)
// #define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U)
// #define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */
/*-------------------------- MPU CAPS ----------------------------------------*/
// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
// #define SOC_MPU_MIN_REGION_SIZE 0x20000000U
// #define SOC_MPU_REGIONS_MAX_NUM 8
// #define SOC_MPU_REGION_RO_SUPPORTED 0
// #define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
// #define SOC_PCNT_GROUPS 1U
// #define SOC_PCNT_UNITS_PER_GROUP 4
// #define SOC_PCNT_CHANNELS_PER_UNIT 2
// #define SOC_PCNT_THRES_POINT_PER_UNIT 2
// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
/*--------------------------- RMT CAPS ---------------------------------------*/
// #define SOC_RMT_GROUPS 1U /*!< One RMT group */
// #define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */
// #define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */
// #define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */
// #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */
// #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */
// #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */
// #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */
// #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */
// #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */
// #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */
// #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */
// #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
// #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */
/*--------------------------- MPI CAPS ---------------------------------------*/
// #define SOC_MPI_MEM_BLOCKS_NUM (4)
// #define SOC_MPI_OPERATIONS_NUM (3)
/*--------------------------- RSA CAPS ---------------------------------------*/
// #define SOC_RSA_MAX_BIT_LEN (3072)
/*--------------------------- SHA CAPS ---------------------------------------*/
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the biggest safe amount of bytes is
31 blocks of 128 bytes = 3968
*/
// #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
// #define SOC_SHA_SUPPORT_DMA (1)
/* The SHA engine is able to resume hashing from a user */
// #define SOC_SHA_SUPPORT_RESUME (1)
/* Has a centralized DMA, which is shared with all peripherals */
// #define SOC_SHA_GDMA (1)
/* Supported HW algorithms */
// #define SOC_SHA_SUPPORT_SHA1 (1)
// #define SOC_SHA_SUPPORT_SHA224 (1)
// #define SOC_SHA_SUPPORT_SHA256 (1)
/*--------------------------- ECDSA CAPS ---------------------------------------*/
// #define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
// #define SOC_SDM_GROUPS 1U
// #define SOC_SDM_CHANNELS_PER_GROUP 4
// #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
// #define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6
// #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
// #define SOC_SPI_SUPPORT_DDRCLK 1
// #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
// #define SOC_SPI_SUPPORT_CD_SIG 1
// #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
// #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
// #define SOC_SPI_SUPPORT_CLK_XTAL 1
// #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
// #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// #define SOC_MEMSPI_IS_INDEPENDENT 1
// #define SOC_SPI_MAX_PRE_DIVIDER 16
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
// #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
// #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
// #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
// #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
// #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
// #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
// #define SOC_SPI_MEM_SUPPORT_WRAP (1)
// #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1
// #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1
// #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
// #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units
// #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units
// #define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
// #define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part
// #define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5
// #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
// #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
// #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
// #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
// #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
// #define SOC_TIMER_SUPPORT_ETM (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
// #define SOC_MWDT_SUPPORT_XTAL (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/
// #define SOC_TWAI_CONTROLLER_NUM 2
// #define SOC_TWAI_CLK_SUPPORT_XTAL 1
// #define SOC_TWAI_BRP_MIN 2
// #define SOC_TWAI_BRP_MAX 32768
// #define SOC_TWAI_SUPPORTS_RX_STATUS 1
/*-------------------------- eFuse CAPS----------------------------*/
// #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
// #define SOC_EFUSE_DIS_PAD_JTAG 1
// #define SOC_EFUSE_DIS_USB_JTAG 1
// #define SOC_EFUSE_DIS_DIRECT_BOOT 1
// #define SOC_EFUSE_SOFT_DIS_JTAG 1
// #define SOC_EFUSE_DIS_ICACHE 1
// #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
/*-------------------------- Secure Boot CAPS----------------------------*/
// #define SOC_SECURE_BOOT_V2_RSA 1
// #define SOC_SECURE_BOOT_V2_ECC 1
// #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3
// #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1
// #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1
/*-------------------------- Flash Encryption CAPS----------------------------*/
// #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
// #define SOC_FLASH_ENCRYPTION_XTS_AES 1
// #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
// #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
/*-------------------------- UART CAPS ---------------------------------------*/
// ESP32-C5 has 3 UARTs (2 HP UART, and 1 LP UART)
#define SOC_UART_NUM (3)
#define SOC_UART_HP_NUM (2)
#define SOC_UART_LP_NUM (1U)
// #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
// #define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
// #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
// #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
// #define SOC_COEX_HW_PTI (1)
/*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/
// #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */
// #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */
/*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/
// #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4)
/*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/
// #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12)
/*-------------------------- Power Management CAPS ----------------------------*/
// #define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
// #define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
// #define SOC_PM_SUPPORT_BT_WAKEUP (1)
// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configue the EXT1 trigger level */
// #define SOC_PM_SUPPORT_CPU_PD (1)
// #define SOC_PM_SUPPORT_MODEM_PD (1)
// #define SOC_PM_SUPPORT_XTAL32K_PD (1)
// #define SOC_PM_SUPPORT_RC32K_PD (1)
// #define SOC_PM_SUPPORT_RC_FAST_PD (1)
// #define SOC_PM_SUPPORT_VDDSDIO_PD (1)
// #define SOC_PM_SUPPORT_TOP_PD (1)
// #define SOC_PM_SUPPORT_HP_AON_PD (1)
// #define SOC_PM_SUPPORT_MAC_BB_PD (1)
// #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
/* macro redefine for pass esp_wifi headers md5sum check */
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
// #define SOC_PM_CPU_RETENTION_BY_SW (1)
// #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
// #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1)
// #define SOC_PM_PAU_LINK_NUM (4)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
// #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
// #define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
// #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
// #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
// #define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */
// #define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
// #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1)
/*------------------------------------ WI-FI CAPS ------------------------------------*/
// #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
// #define SOC_WIFI_FTM_SUPPORT (0) /*!< Support FTM */
// #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */
// #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */
// #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */
// #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */
// #define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */
/*---------------------------------- Bluetooth CAPS ----------------------------------*/
// #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */
// #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */
// #define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */
// #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
// #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
// #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */
// #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */
// #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
// #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */
// #define SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND (1)
/*------------------------------------- PHY CAPS -------------------------------------*/
// #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/

16
components/soc/esp32c5/include/soc/soc_pins.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Pin definition header file. The long term plan is to have a single soc_pins.h for all
* peripherals. Now we temporarily separate these information into periph_pins/channels.h for each
* peripheral and include them here to avoid developing conflicts in those header files.
*/
#pragma once
#include "soc/gpio_pins.h"
#include "soc/spi_pins.h"

82
components/soc/esp32c5/include/soc/spi1_mem_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** SPI1_MEM_CMD_REG register
* SPI1 memory command register
*/
#define SPI1_MEM_CMD_REG (DR_REG_SPI1_MEM_BASE + 0x0)
#define SPI1_MEM_CMD_REG (DR_REG_SPIMEM1_BASE + 0x0)
/** SPI1_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
* The current status of SPI1 master FSM.
*/
@@ -43,7 +43,7 @@ extern "C" {
/** SPI1_MEM_ADDR_REG register
* SPI1 address register
*/
#define SPI1_MEM_ADDR_REG (DR_REG_SPI1_MEM_BASE + 0x4)
#define SPI1_MEM_ADDR_REG (DR_REG_SPIMEM1_BASE + 0x4)
/** SPI1_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
* In user mode, it is the memory address. other then the bit0-bit23 is the memory
* address, the bit24-bit31 are the byte length of a transfer.
@@ -56,7 +56,7 @@ extern "C" {
/** SPI1_MEM_CTRL_REG register
* SPI1 control register.
*/
#define SPI1_MEM_CTRL_REG (DR_REG_SPI1_MEM_BASE + 0x8)
#define SPI1_MEM_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x8)
/** SPI1_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
* In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
* level of SPI bus is output by the MSPI controller.
@@ -171,7 +171,7 @@ extern "C" {
/** SPI1_MEM_CTRL1_REG register
* SPI1 control1 register.
*/
#define SPI1_MEM_CTRL1_REG (DR_REG_SPI1_MEM_BASE + 0xc)
#define SPI1_MEM_CTRL1_REG (DR_REG_SPIMEM1_BASE + 0xc)
/** SPI1_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -185,7 +185,7 @@ extern "C" {
/** SPI1_MEM_CTRL2_REG register
* SPI1 control2 register.
*/
#define SPI1_MEM_CTRL2_REG (DR_REG_SPI1_MEM_BASE + 0x10)
#define SPI1_MEM_CTRL2_REG (DR_REG_SPIMEM1_BASE + 0x10)
/** SPI1_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
* The FSM will be reset.
*/
@@ -197,7 +197,7 @@ extern "C" {
/** SPI1_MEM_CLOCK_REG register
* SPI1 clock division control register.
*/
#define SPI1_MEM_CLOCK_REG (DR_REG_SPI1_MEM_BASE + 0x14)
#define SPI1_MEM_CLOCK_REG (DR_REG_SPIMEM1_BASE + 0x14)
/** SPI1_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_clkcnt_N.
*/
@@ -231,7 +231,7 @@ extern "C" {
/** SPI1_MEM_USER_REG register
* SPI1 user register.
*/
#define SPI1_MEM_USER_REG (DR_REG_SPI1_MEM_BASE + 0x18)
#define SPI1_MEM_USER_REG (DR_REG_SPIMEM1_BASE + 0x18)
/** SPI1_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
* the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
*/
@@ -313,7 +313,7 @@ extern "C" {
/** SPI1_MEM_USER1_REG register
* SPI1 user1 register.
*/
#define SPI1_MEM_USER1_REG (DR_REG_SPI1_MEM_BASE + 0x1c)
#define SPI1_MEM_USER1_REG (DR_REG_SPIMEM1_BASE + 0x1c)
/** SPI1_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
* The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1).
@@ -333,7 +333,7 @@ extern "C" {
/** SPI1_MEM_USER2_REG register
* SPI1 user2 register.
*/
#define SPI1_MEM_USER2_REG (DR_REG_SPI1_MEM_BASE + 0x20)
#define SPI1_MEM_USER2_REG (DR_REG_SPIMEM1_BASE + 0x20)
/** SPI1_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
* The value of command.
*/
@@ -352,7 +352,7 @@ extern "C" {
/** SPI1_MEM_MOSI_DLEN_REG register
* SPI1 send data bit length control register.
*/
#define SPI1_MEM_MOSI_DLEN_REG (DR_REG_SPI1_MEM_BASE + 0x24)
#define SPI1_MEM_MOSI_DLEN_REG (DR_REG_SPIMEM1_BASE + 0x24)
/** SPI1_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
* The length in bits of write-data. The register value shall be (bit_num-1).
*/
@@ -364,7 +364,7 @@ extern "C" {
/** SPI1_MEM_MISO_DLEN_REG register
* SPI1 receive data bit length control register.
*/
#define SPI1_MEM_MISO_DLEN_REG (DR_REG_SPI1_MEM_BASE + 0x28)
#define SPI1_MEM_MISO_DLEN_REG (DR_REG_SPIMEM1_BASE + 0x28)
/** SPI1_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
* The length in bits of read-data. The register value shall be (bit_num-1).
*/
@@ -376,7 +376,7 @@ extern "C" {
/** SPI1_MEM_RD_STATUS_REG register
* SPI1 status register.
*/
#define SPI1_MEM_RD_STATUS_REG (DR_REG_SPI1_MEM_BASE + 0x2c)
#define SPI1_MEM_RD_STATUS_REG (DR_REG_SPIMEM1_BASE + 0x2c)
/** SPI1_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
* The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
*/
@@ -388,7 +388,7 @@ extern "C" {
/** SPI1_MEM_MISC_REG register
* SPI1 misc register
*/
#define SPI1_MEM_MISC_REG (DR_REG_SPI1_MEM_BASE + 0x34)
#define SPI1_MEM_MISC_REG (DR_REG_SPIMEM1_BASE + 0x34)
/** SPI1_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
* SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
* device, such as flash, external RAM and so on.
@@ -423,7 +423,7 @@ extern "C" {
/** SPI1_MEM_W0_REG register
* SPI1 memory data buffer0
*/
#define SPI1_MEM_W0_REG (DR_REG_SPI1_MEM_BASE + 0x58)
#define SPI1_MEM_W0_REG (DR_REG_SPIMEM1_BASE + 0x58)
/** SPI1_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -435,7 +435,7 @@ extern "C" {
/** SPI1_MEM_W1_REG register
* SPI1 memory data buffer1
*/
#define SPI1_MEM_W1_REG (DR_REG_SPI1_MEM_BASE + 0x5c)
#define SPI1_MEM_W1_REG (DR_REG_SPIMEM1_BASE + 0x5c)
/** SPI1_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -447,7 +447,7 @@ extern "C" {
/** SPI1_MEM_W2_REG register
* SPI1 memory data buffer2
*/
#define SPI1_MEM_W2_REG (DR_REG_SPI1_MEM_BASE + 0x60)
#define SPI1_MEM_W2_REG (DR_REG_SPIMEM1_BASE + 0x60)
/** SPI1_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -459,7 +459,7 @@ extern "C" {
/** SPI1_MEM_W3_REG register
* SPI1 memory data buffer3
*/
#define SPI1_MEM_W3_REG (DR_REG_SPI1_MEM_BASE + 0x64)
#define SPI1_MEM_W3_REG (DR_REG_SPIMEM1_BASE + 0x64)
/** SPI1_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -471,7 +471,7 @@ extern "C" {
/** SPI1_MEM_W4_REG register
* SPI1 memory data buffer4
*/
#define SPI1_MEM_W4_REG (DR_REG_SPI1_MEM_BASE + 0x68)
#define SPI1_MEM_W4_REG (DR_REG_SPIMEM1_BASE + 0x68)
/** SPI1_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -483,7 +483,7 @@ extern "C" {
/** SPI1_MEM_W5_REG register
* SPI1 memory data buffer5
*/
#define SPI1_MEM_W5_REG (DR_REG_SPI1_MEM_BASE + 0x6c)
#define SPI1_MEM_W5_REG (DR_REG_SPIMEM1_BASE + 0x6c)
/** SPI1_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -495,7 +495,7 @@ extern "C" {
/** SPI1_MEM_W6_REG register
* SPI1 memory data buffer6
*/
#define SPI1_MEM_W6_REG (DR_REG_SPI1_MEM_BASE + 0x70)
#define SPI1_MEM_W6_REG (DR_REG_SPIMEM1_BASE + 0x70)
/** SPI1_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -507,7 +507,7 @@ extern "C" {
/** SPI1_MEM_W7_REG register
* SPI1 memory data buffer7
*/
#define SPI1_MEM_W7_REG (DR_REG_SPI1_MEM_BASE + 0x74)
#define SPI1_MEM_W7_REG (DR_REG_SPIMEM1_BASE + 0x74)
/** SPI1_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -519,7 +519,7 @@ extern "C" {
/** SPI1_MEM_W8_REG register
* SPI1 memory data buffer8
*/
#define SPI1_MEM_W8_REG (DR_REG_SPI1_MEM_BASE + 0x78)
#define SPI1_MEM_W8_REG (DR_REG_SPIMEM1_BASE + 0x78)
/** SPI1_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -531,7 +531,7 @@ extern "C" {
/** SPI1_MEM_W9_REG register
* SPI1 memory data buffer9
*/
#define SPI1_MEM_W9_REG (DR_REG_SPI1_MEM_BASE + 0x7c)
#define SPI1_MEM_W9_REG (DR_REG_SPIMEM1_BASE + 0x7c)
/** SPI1_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -543,7 +543,7 @@ extern "C" {
/** SPI1_MEM_W10_REG register
* SPI1 memory data buffer10
*/
#define SPI1_MEM_W10_REG (DR_REG_SPI1_MEM_BASE + 0x80)
#define SPI1_MEM_W10_REG (DR_REG_SPIMEM1_BASE + 0x80)
/** SPI1_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -555,7 +555,7 @@ extern "C" {
/** SPI1_MEM_W11_REG register
* SPI1 memory data buffer11
*/
#define SPI1_MEM_W11_REG (DR_REG_SPI1_MEM_BASE + 0x84)
#define SPI1_MEM_W11_REG (DR_REG_SPIMEM1_BASE + 0x84)
/** SPI1_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -567,7 +567,7 @@ extern "C" {
/** SPI1_MEM_W12_REG register
* SPI1 memory data buffer12
*/
#define SPI1_MEM_W12_REG (DR_REG_SPI1_MEM_BASE + 0x88)
#define SPI1_MEM_W12_REG (DR_REG_SPIMEM1_BASE + 0x88)
/** SPI1_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -579,7 +579,7 @@ extern "C" {
/** SPI1_MEM_W13_REG register
* SPI1 memory data buffer13
*/
#define SPI1_MEM_W13_REG (DR_REG_SPI1_MEM_BASE + 0x8c)
#define SPI1_MEM_W13_REG (DR_REG_SPIMEM1_BASE + 0x8c)
/** SPI1_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -591,7 +591,7 @@ extern "C" {
/** SPI1_MEM_W14_REG register
* SPI1 memory data buffer14
*/
#define SPI1_MEM_W14_REG (DR_REG_SPI1_MEM_BASE + 0x90)
#define SPI1_MEM_W14_REG (DR_REG_SPIMEM1_BASE + 0x90)
/** SPI1_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -603,7 +603,7 @@ extern "C" {
/** SPI1_MEM_W15_REG register
* SPI1 memory data buffer15
*/
#define SPI1_MEM_W15_REG (DR_REG_SPI1_MEM_BASE + 0x94)
#define SPI1_MEM_W15_REG (DR_REG_SPIMEM1_BASE + 0x94)
/** SPI1_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -615,7 +615,7 @@ extern "C" {
/** SPI1_MEM_FLASH_WAITI_CTRL_REG register
* SPI1 wait idle control register
*/
#define SPI1_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI1_MEM_BASE + 0x98)
#define SPI1_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x98)
/** SPI1_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
* 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
* Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
@@ -674,7 +674,7 @@ extern "C" {
/** SPI1_MEM_FLASH_SUS_CTRL_REG register
* SPI1 flash suspend control register
*/
#define SPI1_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI1_MEM_BASE + 0x9c)
#define SPI1_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPIMEM1_BASE + 0x9c)
/** SPI1_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
* program erase resume bit, program erase suspend operation will be triggered when
* the bit is set. The bit will be cleared once the operation done.1: enable 0:
@@ -772,7 +772,7 @@ extern "C" {
/** SPI1_MEM_FLASH_SUS_CMD_REG register
* SPI1 flash suspend command register
*/
#define SPI1_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI1_MEM_BASE + 0xa0)
#define SPI1_MEM_FLASH_SUS_CMD_REG (DR_REG_SPIMEM1_BASE + 0xa0)
/** SPI1_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
* Program/Erase suspend command.
*/
@@ -792,7 +792,7 @@ extern "C" {
/** SPI1_MEM_SUS_STATUS_REG register
* SPI1 flash suspend status register
*/
#define SPI1_MEM_SUS_STATUS_REG (DR_REG_SPI1_MEM_BASE + 0xa4)
#define SPI1_MEM_SUS_STATUS_REG (DR_REG_SPIMEM1_BASE + 0xa4)
/** SPI1_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
* The status of flash suspend, only used in SPI1.
*/
@@ -881,7 +881,7 @@ extern "C" {
/** SPI1_MEM_INT_ENA_REG register
* SPI1 interrupt enable register
*/
#define SPI1_MEM_INT_ENA_REG (DR_REG_SPI1_MEM_BASE + 0xc0)
#define SPI1_MEM_INT_ENA_REG (DR_REG_SPIMEM1_BASE + 0xc0)
/** SPI1_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
* The enable bit for SPI1_MEM_PER_END_INT interrupt.
*/
@@ -928,7 +928,7 @@ extern "C" {
/** SPI1_MEM_INT_CLR_REG register
* SPI1 interrupt clear register
*/
#define SPI1_MEM_INT_CLR_REG (DR_REG_SPI1_MEM_BASE + 0xc4)
#define SPI1_MEM_INT_CLR_REG (DR_REG_SPIMEM1_BASE + 0xc4)
/** SPI1_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
* The clear bit for SPI1_MEM_PER_END_INT interrupt.
*/
@@ -975,7 +975,7 @@ extern "C" {
/** SPI1_MEM_INT_RAW_REG register
* SPI1 interrupt raw register
*/
#define SPI1_MEM_INT_RAW_REG (DR_REG_SPI1_MEM_BASE + 0xc8)
#define SPI1_MEM_INT_RAW_REG (DR_REG_SPIMEM1_BASE + 0xc8)
/** SPI1_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* The raw bit for SPI1_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
* command (0x7A) is sent and flash is resumed successfully. 0: Others.
@@ -1031,7 +1031,7 @@ extern "C" {
/** SPI1_MEM_INT_ST_REG register
* SPI1 interrupt status register
*/
#define SPI1_MEM_INT_ST_REG (DR_REG_SPI1_MEM_BASE + 0xcc)
#define SPI1_MEM_INT_ST_REG (DR_REG_SPIMEM1_BASE + 0xcc)
/** SPI1_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
* The status bit for SPI1_MEM_PER_END_INT interrupt.
*/
@@ -1078,7 +1078,7 @@ extern "C" {
/** SPI1_MEM_DDR_REG register
* SPI1 DDR control register
*/
#define SPI1_MEM_DDR_REG (DR_REG_SPI1_MEM_BASE + 0xd4)
#define SPI1_MEM_DDR_REG (DR_REG_SPIMEM1_BASE + 0xd4)
/** SPI1_MEM_F_DDR_EN : HRO; bitpos: [0]; default: 0;
* 1: in ddr mode, 0 in sdr mode
*/
@@ -1187,7 +1187,7 @@ extern "C" {
/** SPI1_MEM_TIMING_CALI_REG register
* SPI1 timing control register
*/
#define SPI1_MEM_TIMING_CALI_REG (DR_REG_SPI1_MEM_BASE + 0x180)
#define SPI1_MEM_TIMING_CALI_REG (DR_REG_SPIMEM1_BASE + 0x180)
/** SPI1_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
* The bit is used to enable timing auto-calibration for all reading operations.
*/
@@ -1206,7 +1206,7 @@ extern "C" {
/** SPI1_MEM_CLOCK_GATE_REG register
* SPI1 clk_gate register
*/
#define SPI1_MEM_CLOCK_GATE_REG (DR_REG_SPI1_MEM_BASE + 0x200)
#define SPI1_MEM_CLOCK_GATE_REG (DR_REG_SPIMEM1_BASE + 0x200)
/** SPI1_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
* Register clock gate enable signal. 1: Enable. 0: Disable.
*/
@@ -1218,7 +1218,7 @@ extern "C" {
/** SPI1_MEM_DATE_REG register
* Version control register
*/
#define SPI1_MEM_DATE_REG (DR_REG_SPI1_MEM_BASE + 0x3fc)
#define SPI1_MEM_DATE_REG (DR_REG_SPIMEM1_BASE + 0x3fc)
/** SPI1_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128;
* Version control register
*/

146
components/soc/esp32c5/include/soc/spi_mem_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** SPI_MEM_CMD_REG register
* SPI0 FSM status register
*/
#define SPI_MEM_CMD_REG (DR_REG_SPI_BASE + 0x0)
#define SPI_MEM_CMD_REG (DR_REG_SPIMEM0_BASE + 0x0)
/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
* The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT ,
* 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent
@@ -46,7 +46,7 @@ extern "C" {
/** SPI_MEM_CTRL_REG register
* SPI0 control register.
*/
#define SPI_MEM_CTRL_REG (DR_REG_SPI_BASE + 0x8)
#define SPI_MEM_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x8)
/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0;
* In the dummy phase of an MSPI write data transfer when accesses to flash, the level
* of SPI_DQS is output by the MSPI controller.
@@ -195,7 +195,7 @@ extern "C" {
/** SPI_MEM_CTRL1_REG register
* SPI0 control1 register.
*/
#define SPI_MEM_CTRL1_REG (DR_REG_SPI_BASE + 0xc)
#define SPI_MEM_CTRL1_REG (DR_REG_SPIMEM0_BASE + 0xc)
/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -298,7 +298,7 @@ extern "C" {
/** SPI_MEM_CTRL2_REG register
* SPI0 control2 register.
*/
#define SPI_MEM_CTRL2_REG (DR_REG_SPI_BASE + 0x10)
#define SPI_MEM_CTRL2_REG (DR_REG_SPIMEM0_BASE + 0x10)
/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1;
* (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with
* SPI_MEM_CS_SETUP bit.
@@ -368,7 +368,7 @@ extern "C" {
/** SPI_MEM_CLOCK_REG register
* SPI clock division control register.
*/
#define SPI_MEM_CLOCK_REG (DR_REG_SPI_BASE + 0x14)
#define SPI_MEM_CLOCK_REG (DR_REG_SPIMEM0_BASE + 0x14)
/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
* In the master mode it must be equal to spi_mem_clkcnt_N.
*/
@@ -403,7 +403,7 @@ extern "C" {
/** SPI_MEM_USER_REG register
* SPI0 user register.
*/
#define SPI_MEM_USER_REG (DR_REG_SPI_BASE + 0x18)
#define SPI_MEM_USER_REG (DR_REG_SPIMEM0_BASE + 0x18)
/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0;
* spi cs keep low when spi is in done phase. 1: enable 0: disable.
*/
@@ -443,7 +443,7 @@ extern "C" {
/** SPI_MEM_USER1_REG register
* SPI0 user1 register.
*/
#define SPI_MEM_USER1_REG (DR_REG_SPI_BASE + 0x1c)
#define SPI_MEM_USER1_REG (DR_REG_SPIMEM0_BASE + 0x1c)
/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
* The length in spi_mem_clk cycles of dummy phase. The register value shall be
* (cycle_num-1).
@@ -470,7 +470,7 @@ extern "C" {
/** SPI_MEM_USER2_REG register
* SPI0 user2 register.
*/
#define SPI_MEM_USER2_REG (DR_REG_SPI_BASE + 0x20)
#define SPI_MEM_USER2_REG (DR_REG_SPIMEM0_BASE + 0x20)
/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
* The value of command.
*/
@@ -489,7 +489,7 @@ extern "C" {
/** SPI_MEM_MISC_REG register
* SPI0 misc register
*/
#define SPI_MEM_MISC_REG (DR_REG_SPI_BASE + 0x34)
#define SPI_MEM_MISC_REG (DR_REG_SPIMEM0_BASE + 0x34)
/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0;
* For SPI0, flash is connected to SUBPINs.
*/
@@ -522,7 +522,7 @@ extern "C" {
/** SPI_MEM_CACHE_FCTRL_REG register
* SPI0 bit mode control register.
*/
#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_BASE + 0x3c)
#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPIMEM0_BASE + 0x3c)
/** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1;
* Set this bit to check AXI read/write the same address region.
*/
@@ -542,7 +542,7 @@ extern "C" {
/** SPI_MEM_SRAM_CMD_REG register
* SPI0 external RAM mode control register
*/
#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI_BASE + 0x44)
#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPIMEM0_BASE + 0x44)
/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0;
* In the dummy phase of an MSPI write data transfer when accesses to external RAM,
* the level of SPI_DQS is output by the MSPI controller.
@@ -579,7 +579,7 @@ extern "C" {
/** SPI_MEM_FSM_REG register
* SPI0 FSM status register
*/
#define SPI_MEM_FSM_REG (DR_REG_SPI_BASE + 0x54)
#define SPI_MEM_FSM_REG (DR_REG_SPIMEM0_BASE + 0x54)
/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4;
* The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
*/
@@ -591,7 +591,7 @@ extern "C" {
/** SPI_MEM_INT_ENA_REG register
* SPI0 interrupt enable register
*/
#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_BASE + 0xc0)
#define SPI_MEM_INT_ENA_REG (DR_REG_SPIMEM0_BASE + 0xc0)
/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0;
* The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
*/
@@ -645,7 +645,7 @@ extern "C" {
/** SPI_MEM_INT_CLR_REG register
* SPI0 interrupt clear register
*/
#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_BASE + 0xc4)
#define SPI_MEM_INT_CLR_REG (DR_REG_SPIMEM0_BASE + 0xc4)
/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0;
* The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
*/
@@ -699,7 +699,7 @@ extern "C" {
/** SPI_MEM_INT_RAW_REG register
* SPI0 interrupt raw register
*/
#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_BASE + 0xc8)
#define SPI_MEM_INT_RAW_REG (DR_REG_SPIMEM0_BASE + 0xc8)
/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
* The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is
* changed from non idle state to idle state. It means that SPI_CS raises high. 0:
@@ -769,7 +769,7 @@ extern "C" {
/** SPI_MEM_INT_ST_REG register
* SPI0 interrupt status register
*/
#define SPI_MEM_INT_ST_REG (DR_REG_SPI_BASE + 0xcc)
#define SPI_MEM_INT_ST_REG (DR_REG_SPIMEM0_BASE + 0xcc)
/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0;
* The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
*/
@@ -823,7 +823,7 @@ extern "C" {
/** SPI_MEM_DDR_REG register
* SPI0 flash DDR mode control register
*/
#define SPI_MEM_DDR_REG (DR_REG_SPI_BASE + 0xd4)
#define SPI_MEM_DDR_REG (DR_REG_SPIMEM0_BASE + 0xd4)
/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
* 1: in DDR mode, 0 in SDR mode
*/
@@ -948,7 +948,7 @@ extern "C" {
/** SPI_SMEM_DDR_REG register
* SPI0 external RAM DDR mode control register
*/
#define SPI_SMEM_DDR_REG (DR_REG_SPI_BASE + 0xd8)
#define SPI_SMEM_DDR_REG (DR_REG_SPIMEM0_BASE + 0xd8)
/** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0;
* 1: in DDR mode, 0 in SDR mode
*/
@@ -1074,7 +1074,7 @@ extern "C" {
/** SPI_FMEM_PMS0_ATTR_REG register
* MSPI flash PMS section 0 attribute register
*/
#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x100)
#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x100)
/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed.
*/
@@ -1102,7 +1102,7 @@ extern "C" {
/** SPI_FMEM_PMS1_ATTR_REG register
* MSPI flash PMS section 1 attribute register
*/
#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x104)
#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x104)
/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed.
*/
@@ -1130,7 +1130,7 @@ extern "C" {
/** SPI_FMEM_PMS2_ATTR_REG register
* MSPI flash PMS section 2 attribute register
*/
#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x108)
#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x108)
/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed.
*/
@@ -1158,7 +1158,7 @@ extern "C" {
/** SPI_FMEM_PMS3_ATTR_REG register
* MSPI flash PMS section 3 attribute register
*/
#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x10c)
#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x10c)
/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed.
*/
@@ -1186,7 +1186,7 @@ extern "C" {
/** SPI_FMEM_PMS0_ADDR_REG register
* SPI1 flash PMS section 0 start address register
*/
#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x110)
#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x110)
/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 flash PMS section 0 start address value
*/
@@ -1198,7 +1198,7 @@ extern "C" {
/** SPI_FMEM_PMS1_ADDR_REG register
* SPI1 flash PMS section 1 start address register
*/
#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x114)
#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x114)
/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 flash PMS section 1 start address value
*/
@@ -1210,7 +1210,7 @@ extern "C" {
/** SPI_FMEM_PMS2_ADDR_REG register
* SPI1 flash PMS section 2 start address register
*/
#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x118)
#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x118)
/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 flash PMS section 2 start address value
*/
@@ -1222,7 +1222,7 @@ extern "C" {
/** SPI_FMEM_PMS3_ADDR_REG register
* SPI1 flash PMS section 3 start address register
*/
#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x11c)
#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x11c)
/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 flash PMS section 3 start address value
*/
@@ -1234,7 +1234,7 @@ extern "C" {
/** SPI_FMEM_PMS0_SIZE_REG register
* SPI1 flash PMS section 0 start address register
*/
#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x120)
#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x120)
/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S,
* SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE)
@@ -1247,7 +1247,7 @@ extern "C" {
/** SPI_FMEM_PMS1_SIZE_REG register
* SPI1 flash PMS section 1 start address register
*/
#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x124)
#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x124)
/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S,
* SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE)
@@ -1260,7 +1260,7 @@ extern "C" {
/** SPI_FMEM_PMS2_SIZE_REG register
* SPI1 flash PMS section 2 start address register
*/
#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x128)
#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x128)
/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S,
* SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE)
@@ -1273,7 +1273,7 @@ extern "C" {
/** SPI_FMEM_PMS3_SIZE_REG register
* SPI1 flash PMS section 3 start address register
*/
#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x12c)
#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x12c)
/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S,
* SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE)
@@ -1286,7 +1286,7 @@ extern "C" {
/** SPI_SMEM_PMS0_ATTR_REG register
* SPI1 flash PMS section 0 start address register
*/
#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x130)
#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x130)
/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed.
*/
@@ -1314,7 +1314,7 @@ extern "C" {
/** SPI_SMEM_PMS1_ATTR_REG register
* SPI1 flash PMS section 1 start address register
*/
#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x134)
#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x134)
/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed.
*/
@@ -1342,7 +1342,7 @@ extern "C" {
/** SPI_SMEM_PMS2_ATTR_REG register
* SPI1 flash PMS section 2 start address register
*/
#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x138)
#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x138)
/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed.
*/
@@ -1370,7 +1370,7 @@ extern "C" {
/** SPI_SMEM_PMS3_ATTR_REG register
* SPI1 flash PMS section 3 start address register
*/
#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x13c)
#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPIMEM0_BASE + 0x13c)
/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1;
* 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed.
*/
@@ -1398,7 +1398,7 @@ extern "C" {
/** SPI_SMEM_PMS0_ADDR_REG register
* SPI1 external RAM PMS section 0 start address register
*/
#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x140)
#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x140)
/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 external RAM PMS section 0 start address value
*/
@@ -1410,7 +1410,7 @@ extern "C" {
/** SPI_SMEM_PMS1_ADDR_REG register
* SPI1 external RAM PMS section 1 start address register
*/
#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x144)
#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x144)
/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 external RAM PMS section 1 start address value
*/
@@ -1422,7 +1422,7 @@ extern "C" {
/** SPI_SMEM_PMS2_ADDR_REG register
* SPI1 external RAM PMS section 2 start address register
*/
#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x148)
#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x148)
/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 external RAM PMS section 2 start address value
*/
@@ -1434,7 +1434,7 @@ extern "C" {
/** SPI_SMEM_PMS3_ADDR_REG register
* SPI1 external RAM PMS section 3 start address register
*/
#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x14c)
#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x14c)
/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0;
* SPI1 external RAM PMS section 3 start address value
*/
@@ -1446,7 +1446,7 @@ extern "C" {
/** SPI_SMEM_PMS0_SIZE_REG register
* SPI1 external RAM PMS section 0 start address register
*/
#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x150)
#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x150)
/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S,
* SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE)
@@ -1459,7 +1459,7 @@ extern "C" {
/** SPI_SMEM_PMS1_SIZE_REG register
* SPI1 external RAM PMS section 1 start address register
*/
#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x154)
#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x154)
/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S,
* SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE)
@@ -1472,7 +1472,7 @@ extern "C" {
/** SPI_SMEM_PMS2_SIZE_REG register
* SPI1 external RAM PMS section 2 start address register
*/
#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x158)
#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x158)
/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S,
* SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE)
@@ -1485,7 +1485,7 @@ extern "C" {
/** SPI_SMEM_PMS3_SIZE_REG register
* SPI1 external RAM PMS section 3 start address register
*/
#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x15c)
#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPIMEM0_BASE + 0x15c)
/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096;
* SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S,
* SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE)
@@ -1498,7 +1498,7 @@ extern "C" {
/** SPI_MEM_PMS_REJECT_REG register
* SPI1 access reject register
*/
#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI_BASE + 0x164)
#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPIMEM0_BASE + 0x164)
/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
* This bits show the first SPI1 access error address. It is cleared by when
* SPI_MEM_PMS_REJECT_INT_CLR bit is set.
@@ -1550,7 +1550,7 @@ extern "C" {
/** SPI_MEM_ECC_CTRL_REG register
* MSPI ECC control register
*/
#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x168)
#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x168)
/** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0;
* This bits show the error times of MSPI ECC read. It is cleared by when
* SPI_MEM_ECC_ERR_INT_CLR bit is set.
@@ -1618,7 +1618,7 @@ extern "C" {
/** SPI_MEM_ECC_ERR_ADDR_REG register
* MSPI ECC error address register
*/
#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x16c)
#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x16c)
/** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0;
* This bits show the first MSPI ECC error address. It is cleared by when
* SPI_MEM_ECC_ERR_INT_CLR bit is set.
@@ -1631,7 +1631,7 @@ extern "C" {
/** SPI_MEM_AXI_ERR_ADDR_REG register
* SPI0 AXI request error address.
*/
#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x170)
#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPIMEM0_BASE + 0x170)
/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0;
* This bits show the first AXI write/read invalid error or AXI write flash error
* address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR,
@@ -1645,7 +1645,7 @@ extern "C" {
/** SPI_SMEM_ECC_CTRL_REG register
* MSPI ECC control register
*/
#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x174)
#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x174)
/** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0;
* Set this bit to calculate the error times of MSPI ECC read when accesses to
* external RAM.
@@ -1675,7 +1675,7 @@ extern "C" {
/** SPI_SMEM_AXI_ADDR_CTRL_REG register
* SPI0 AXI address control register
*/
#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI_BASE + 0x178)
#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x178)
/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1;
* The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
* and SPI0 transfers are done. 0: Others.
@@ -1724,7 +1724,7 @@ extern "C" {
/** SPI_MEM_AXI_ERR_RESP_EN_REG register
* SPI0 AXI error response enable register
*/
#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI_BASE + 0x17c)
#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPIMEM0_BASE + 0x17c)
/** SPI_MEM_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0;
* Set this bit to enable AXI response function for mmu valid err in axi write trans.
*/
@@ -1814,7 +1814,7 @@ extern "C" {
/** SPI_MEM_TIMING_CALI_REG register
* SPI0 flash timing calibration register
*/
#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x180)
#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPIMEM0_BASE + 0x180)
/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1;
* The bit is used to enable timing adjust clock for all reading operations.
*/
@@ -1855,7 +1855,7 @@ extern "C" {
/** SPI_MEM_DIN_MODE_REG register
* MSPI flash input timing delay mode control register
*/
#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x184)
#define SPI_MEM_DIN_MODE_REG (DR_REG_SPIMEM0_BASE + 0x184)
/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0;
* the input signals are delayed by system clock cycles, 0: input without delayed, 1:
* input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
@@ -1945,7 +1945,7 @@ extern "C" {
/** SPI_MEM_DIN_NUM_REG register
* MSPI flash input timing delay number control register
*/
#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x188)
#define SPI_MEM_DIN_NUM_REG (DR_REG_SPIMEM0_BASE + 0x188)
/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
* the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,...
@@ -2022,7 +2022,7 @@ extern "C" {
/** SPI_MEM_DOUT_MODE_REG register
* MSPI flash output timing adjustment control register
*/
#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x18c)
#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPIMEM0_BASE + 0x18c)
/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
* the output signals are delayed by system clock cycles, 0: output without delayed,
* 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
@@ -2112,7 +2112,7 @@ extern "C" {
/** SPI_SMEM_TIMING_CALI_REG register
* MSPI external RAM timing calibration register
*/
#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x190)
#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPIMEM0_BASE + 0x190)
/** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1;
* For sram, the bit is used to enable timing adjust clock for all reading operations.
*/
@@ -2147,7 +2147,7 @@ extern "C" {
/** SPI_SMEM_DIN_MODE_REG register
* MSPI external RAM input timing delay mode control register
*/
#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x194)
#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPIMEM0_BASE + 0x194)
/** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0;
* the input signals are delayed by system clock cycles, 0: input without delayed, 1:
* input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
@@ -2242,7 +2242,7 @@ extern "C" {
/** SPI_SMEM_DIN_NUM_REG register
* MSPI external RAM input timing delay number control register
*/
#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x198)
#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPIMEM0_BASE + 0x198)
/** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0;
* the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,...
@@ -2319,7 +2319,7 @@ extern "C" {
/** SPI_SMEM_DOUT_MODE_REG register
* MSPI external RAM output timing adjustment control register
*/
#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x19c)
#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPIMEM0_BASE + 0x19c)
/** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0;
* the output signals are delayed by system clock cycles, 0: output without delayed,
* 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
@@ -2414,7 +2414,7 @@ extern "C" {
/** SPI_SMEM_AC_REG register
* MSPI external RAM ECC and SPI CS timing control register
*/
#define SPI_SMEM_AC_REG (DR_REG_SPI_BASE + 0x1a0)
#define SPI_SMEM_AC_REG (DR_REG_SPIMEM0_BASE + 0x1a0)
/** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0;
* For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0:
* disable.
@@ -2492,7 +2492,7 @@ extern "C" {
/** SPI_MEM_CLOCK_GATE_REG register
* SPI0 clock gate register
*/
#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_BASE + 0x200)
#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPIMEM0_BASE + 0x200)
/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1;
* Register clock gate enable signal. 1: Enable. 0: Disable.
*/
@@ -2504,7 +2504,7 @@ extern "C" {
/** SPI_MEM_XTS_PLAIN_BASE_REG register
* The base address of the memory that stores plaintext in Manual Encryption
*/
#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI_BASE + 0x300)
#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPIMEM0_BASE + 0x300)
/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0;
* This field is only used to generate include file in c case. This field is useless.
* Please do not use this field.
@@ -2517,7 +2517,7 @@ extern "C" {
/** SPI_MEM_XTS_LINESIZE_REG register
* Manual Encryption Line-Size register
*/
#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI_BASE + 0x340)
#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPIMEM0_BASE + 0x340)
/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0;
* This bits stores the line-size parameter which will be used in manual encryption
* calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1:
@@ -2531,7 +2531,7 @@ extern "C" {
/** SPI_MEM_XTS_DESTINATION_REG register
* Manual Encryption destination register
*/
#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI_BASE + 0x344)
#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPIMEM0_BASE + 0x344)
/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0;
* This bit stores the destination parameter which will be used in manual encryption
* calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.
@@ -2544,7 +2544,7 @@ extern "C" {
/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register
* Manual Encryption physical address register
*/
#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI_BASE + 0x348)
#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPIMEM0_BASE + 0x348)
/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [25:0]; default: 0;
* This bits stores the physical-address parameter which will be used in manual
* encryption calculation. This value should aligned with byte number decided by
@@ -2558,7 +2558,7 @@ extern "C" {
/** SPI_MEM_XTS_TRIGGER_REG register
* Manual Encryption physical address register
*/
#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI_BASE + 0x34c)
#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPIMEM0_BASE + 0x34c)
/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0;
* Set this bit to trigger the process of manual encryption calculation. This action
* should only be asserted when manual encryption status is 0. After this action,
@@ -2573,7 +2573,7 @@ extern "C" {
/** SPI_MEM_XTS_RELEASE_REG register
* Manual Encryption physical address register
*/
#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI_BASE + 0x350)
#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPIMEM0_BASE + 0x350)
/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0;
* Set this bit to release encrypted result to mspi. This action should only be
* asserted when manual encryption status is 2. After this action, manual encryption
@@ -2587,7 +2587,7 @@ extern "C" {
/** SPI_MEM_XTS_DESTROY_REG register
* Manual Encryption physical address register
*/
#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI_BASE + 0x354)
#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPIMEM0_BASE + 0x354)
/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0;
* Set this bit to destroy encrypted result. This action should be asserted only when
* manual encryption status is 3. After this action, manual encryption status will
@@ -2601,7 +2601,7 @@ extern "C" {
/** SPI_MEM_XTS_STATE_REG register
* Manual Encryption physical address register
*/
#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI_BASE + 0x358)
#define SPI_MEM_XTS_STATE_REG (DR_REG_SPIMEM0_BASE + 0x358)
/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0;
* This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
* calculation, 2: encryption calculation is done but the encrypted result is
@@ -2615,7 +2615,7 @@ extern "C" {
/** SPI_MEM_XTS_DATE_REG register
* Manual Encryption version register
*/
#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI_BASE + 0x35c)
#define SPI_MEM_XTS_DATE_REG (DR_REG_SPIMEM0_BASE + 0x35c)
/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 538972176;
* This bits stores the last modified-time of manual encryption feature.
*/
@@ -2627,7 +2627,7 @@ extern "C" {
/** SPI_MEM_MMU_ITEM_CONTENT_REG register
* MSPI-MMU item content register
*/
#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI_BASE + 0x37c)
#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPIMEM0_BASE + 0x37c)
/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892;
* MSPI-MMU item content
*/
@@ -2639,7 +2639,7 @@ extern "C" {
/** SPI_MEM_MMU_ITEM_INDEX_REG register
* MSPI-MMU item index register
*/
#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI_BASE + 0x380)
#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPIMEM0_BASE + 0x380)
/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0;
* MSPI-MMU item index
*/
@@ -2651,7 +2651,7 @@ extern "C" {
/** SPI_MEM_MMU_POWER_CTRL_REG register
* MSPI MMU power control register
*/
#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI_BASE + 0x384)
#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x384)
/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Set this bit to enable mmu-memory clock force on
*/
@@ -2692,7 +2692,7 @@ extern "C" {
/** SPI_MEM_DPA_CTRL_REG register
* SPI memory cryption DPA register
*/
#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI_BASE + 0x388)
#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPIMEM0_BASE + 0x388)
/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
* Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
* The bigger the number is, the more secure the cryption is. (Note that the
@@ -2723,7 +2723,7 @@ extern "C" {
/** SPI_MEM_DATE_REG register
* SPI0 version control register
*/
#define SPI_MEM_DATE_REG (DR_REG_SPI_BASE + 0x3fc)
#define SPI_MEM_DATE_REG (DR_REG_SPIMEM0_BASE + 0x3fc)
/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36712560;
* SPI0 register version.
*/

25
components/soc/esp32c5/include/soc/spi_pins.h Normal file
View File

@@ -0,0 +1,25 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
// TODO: [ESP32C5] IDF-8698 (inherit from C6)
#define SPI_FUNC_NUM 0
#define SPI_IOMUX_PIN_NUM_CS 24
#define SPI_IOMUX_PIN_NUM_CLK 29
#define SPI_IOMUX_PIN_NUM_MOSI 30
#define SPI_IOMUX_PIN_NUM_MISO 25
#define SPI_IOMUX_PIN_NUM_WP 26
#define SPI_IOMUX_PIN_NUM_HD 28
#define SPI2_FUNC_NUM 2
#define SPI2_IOMUX_PIN_NUM_MISO 2
#define SPI2_IOMUX_PIN_NUM_HD 4
#define SPI2_IOMUX_PIN_NUM_WP 5
#define SPI2_IOMUX_PIN_NUM_CLK 6
#define SPI2_IOMUX_PIN_NUM_MOSI 7
#define SPI2_IOMUX_PIN_NUM_CS 16

76
components/soc/esp32c5/include/soc/spi_reg.h
View File

@@ -14,7 +14,7 @@ extern "C" {
/** SPI_CMD_REG register
* Command control register
*/
#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
#define SPI_CMD_REG (DR_REG_GPSPI2_BASE + 0x0)
/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
* Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
*/
@@ -43,7 +43,7 @@ extern "C" {
/** SPI_ADDR_REG register
* Address value register
*/
#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4)
#define SPI_ADDR_REG (DR_REG_GPSPI2_BASE + 0x4)
/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
* Address to slave. Can be configured in CONF state.
*/
@@ -55,7 +55,7 @@ extern "C" {
/** SPI_CTRL_REG register
* SPI control register
*/
#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8)
#define SPI_CTRL_REG (DR_REG_GPSPI2_BASE + 0x8)
/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
* 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
* the FSPI bus signals are output. Can be configured in CONF state.
@@ -188,7 +188,7 @@ extern "C" {
/** SPI_CLOCK_REG register
* SPI clock control register
*/
#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc)
#define SPI_CLOCK_REG (DR_REG_GPSPI2_BASE + 0xc)
/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
* In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
* 0. Can be configured in CONF state.
@@ -232,7 +232,7 @@ extern "C" {
/** SPI_USER_REG register
* SPI USER control register
*/
#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10)
#define SPI_USER_REG (DR_REG_GPSPI2_BASE + 0x10)
/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
* Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
* configured in CONF state.
@@ -403,7 +403,7 @@ extern "C" {
/** SPI_USER1_REG register
* SPI USER control register 1
*/
#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14)
#define SPI_USER1_REG (DR_REG_GPSPI2_BASE + 0x14)
/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
* The length in spi_clk cycles of dummy phase. The register value shall be
* (cycle_num-1). Can be configured in CONF state.
@@ -449,7 +449,7 @@ extern "C" {
/** SPI_USER2_REG register
* SPI USER control register 2
*/
#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18)
#define SPI_USER2_REG (DR_REG_GPSPI2_BASE + 0x18)
/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
* The value of command. Can be configured in CONF state.
*/
@@ -478,7 +478,7 @@ extern "C" {
/** SPI_MS_DLEN_REG register
* SPI data bit length control register
*/
#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c)
#define SPI_MS_DLEN_REG (DR_REG_GPSPI2_BASE + 0x1c)
/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
* The value of these bits is the configured SPI transmission data bit length in
* master mode DMA controlled transfer or CPU controlled transfer. The value is also
@@ -493,7 +493,7 @@ extern "C" {
/** SPI_MISC_REG register
* SPI misc register
*/
#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20)
#define SPI_MISC_REG (DR_REG_GPSPI2_BASE + 0x20)
/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
* SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
* be configured in CONF state.
@@ -634,7 +634,7 @@ extern "C" {
/** SPI_DIN_MODE_REG register
* SPI input delay mode configuration
*/
#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24)
#define SPI_DIN_MODE_REG (DR_REG_GPSPI2_BASE + 0x24)
/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: input without delayed,
* 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
@@ -719,7 +719,7 @@ extern "C" {
/** SPI_DIN_NUM_REG register
* SPI input delay number configuration
*/
#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28)
#define SPI_DIN_NUM_REG (DR_REG_GPSPI2_BASE + 0x28)
/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
* the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
* delayed by 2 cycles,... Can be configured in CONF state.
@@ -788,7 +788,7 @@ extern "C" {
/** SPI_DOUT_MODE_REG register
* SPI output delay mode configuration
*/
#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c)
#define SPI_DOUT_MODE_REG (DR_REG_GPSPI2_BASE + 0x2c)
/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
* The output signal $n is delayed by the SPI module clock, 0: output without delayed,
* 1: output delay for a SPI module clock cycle at its negative edge. Can be
@@ -874,7 +874,7 @@ extern "C" {
/** SPI_DMA_CONF_REG register
* SPI DMA control register
*/
#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30)
#define SPI_DMA_CONF_REG (DR_REG_GPSPI2_BASE + 0x30)
/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
* Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
* DMA TX FIFO is ready for sending data.
@@ -966,7 +966,7 @@ extern "C" {
/** SPI_DMA_INT_ENA_REG register
* SPI interrupt enable register
*/
#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34)
#define SPI_DMA_INT_ENA_REG (DR_REG_GPSPI2_BASE + 0x34)
/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
* The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
@@ -1118,7 +1118,7 @@ extern "C" {
/** SPI_DMA_INT_CLR_REG register
* SPI interrupt clear register
*/
#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38)
#define SPI_DMA_INT_CLR_REG (DR_REG_GPSPI2_BASE + 0x38)
/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
* The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
@@ -1270,7 +1270,7 @@ extern "C" {
/** SPI_DMA_INT_RAW_REG register
* SPI interrupt raw register
*/
#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c)
#define SPI_DMA_INT_RAW_REG (DR_REG_GPSPI2_BASE + 0x3c)
/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
* 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
* receive data. 0: Others.
@@ -1444,7 +1444,7 @@ extern "C" {
/** SPI_DMA_INT_ST_REG register
* SPI interrupt status register
*/
#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40)
#define SPI_DMA_INT_ST_REG (DR_REG_GPSPI2_BASE + 0x40)
/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
* The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
@@ -1596,7 +1596,7 @@ extern "C" {
/** SPI_DMA_INT_SET_REG register
* SPI interrupt software set register
*/
#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44)
#define SPI_DMA_INT_SET_REG (DR_REG_GPSPI2_BASE + 0x44)
/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
* The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
*/
@@ -1748,7 +1748,7 @@ extern "C" {
/** SPI_W0_REG register
* SPI CPU-controlled buffer0
*/
#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98)
#define SPI_W0_REG (DR_REG_GPSPI2_BASE + 0x98)
/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1760,7 +1760,7 @@ extern "C" {
/** SPI_W1_REG register
* SPI CPU-controlled buffer1
*/
#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c)
#define SPI_W1_REG (DR_REG_GPSPI2_BASE + 0x9c)
/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1772,7 +1772,7 @@ extern "C" {
/** SPI_W2_REG register
* SPI CPU-controlled buffer2
*/
#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0)
#define SPI_W2_REG (DR_REG_GPSPI2_BASE + 0xa0)
/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1784,7 +1784,7 @@ extern "C" {
/** SPI_W3_REG register
* SPI CPU-controlled buffer3
*/
#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4)
#define SPI_W3_REG (DR_REG_GPSPI2_BASE + 0xa4)
/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1796,7 +1796,7 @@ extern "C" {
/** SPI_W4_REG register
* SPI CPU-controlled buffer4
*/
#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8)
#define SPI_W4_REG (DR_REG_GPSPI2_BASE + 0xa8)
/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1808,7 +1808,7 @@ extern "C" {
/** SPI_W5_REG register
* SPI CPU-controlled buffer5
*/
#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac)
#define SPI_W5_REG (DR_REG_GPSPI2_BASE + 0xac)
/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1820,7 +1820,7 @@ extern "C" {
/** SPI_W6_REG register
* SPI CPU-controlled buffer6
*/
#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0)
#define SPI_W6_REG (DR_REG_GPSPI2_BASE + 0xb0)
/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1832,7 +1832,7 @@ extern "C" {
/** SPI_W7_REG register
* SPI CPU-controlled buffer7
*/
#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4)
#define SPI_W7_REG (DR_REG_GPSPI2_BASE + 0xb4)
/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1844,7 +1844,7 @@ extern "C" {
/** SPI_W8_REG register
* SPI CPU-controlled buffer8
*/
#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8)
#define SPI_W8_REG (DR_REG_GPSPI2_BASE + 0xb8)
/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1856,7 +1856,7 @@ extern "C" {
/** SPI_W9_REG register
* SPI CPU-controlled buffer9
*/
#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc)
#define SPI_W9_REG (DR_REG_GPSPI2_BASE + 0xbc)
/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1868,7 +1868,7 @@ extern "C" {
/** SPI_W10_REG register
* SPI CPU-controlled buffer10
*/
#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0)
#define SPI_W10_REG (DR_REG_GPSPI2_BASE + 0xc0)
/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1880,7 +1880,7 @@ extern "C" {
/** SPI_W11_REG register
* SPI CPU-controlled buffer11
*/
#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4)
#define SPI_W11_REG (DR_REG_GPSPI2_BASE + 0xc4)
/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1892,7 +1892,7 @@ extern "C" {
/** SPI_W12_REG register
* SPI CPU-controlled buffer12
*/
#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8)
#define SPI_W12_REG (DR_REG_GPSPI2_BASE + 0xc8)
/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1904,7 +1904,7 @@ extern "C" {
/** SPI_W13_REG register
* SPI CPU-controlled buffer13
*/
#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc)
#define SPI_W13_REG (DR_REG_GPSPI2_BASE + 0xcc)
/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1916,7 +1916,7 @@ extern "C" {
/** SPI_W14_REG register
* SPI CPU-controlled buffer14
*/
#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0)
#define SPI_W14_REG (DR_REG_GPSPI2_BASE + 0xd0)
/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1928,7 +1928,7 @@ extern "C" {
/** SPI_W15_REG register
* SPI CPU-controlled buffer15
*/
#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4)
#define SPI_W15_REG (DR_REG_GPSPI2_BASE + 0xd4)
/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
* data buffer
*/
@@ -1940,7 +1940,7 @@ extern "C" {
/** SPI_SLAVE_REG register
* SPI slave control register
*/
#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0)
#define SPI_SLAVE_REG (DR_REG_GPSPI2_BASE + 0xe0)
/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
* SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
* one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -2049,7 +2049,7 @@ extern "C" {
/** SPI_SLAVE1_REG register
* SPI slave control register 1
*/
#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4)
#define SPI_SLAVE1_REG (DR_REG_GPSPI2_BASE + 0xe4)
/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
* The transferred data bit length in SPI slave FD and HD mode.
*/
@@ -2075,7 +2075,7 @@ extern "C" {
/** SPI_CLK_GATE_REG register
* SPI module clock and register clock control
*/
#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8)
#define SPI_CLK_GATE_REG (DR_REG_GPSPI2_BASE + 0xe8)
/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
* Set this bit to enable clk gate
*/
@@ -2102,7 +2102,7 @@ extern "C" {
/** SPI_DATE_REG register
* Version control
*/
#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0)
#define SPI_DATE_REG (DR_REG_GPSPI2_BASE + 0xf0)
/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931;
* SPI register version.
*/