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feat(esp32c5): support esp32c5 g0 components
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@@ -61,8 +61,8 @@ typedef enum {
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ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
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ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
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ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
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ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/
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ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/
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ETS_TWAI0_INTR_SOURCE, /**< interrupt of twai0, level*/
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ETS_TWAI1_INTR_SOURCE, /**< interrupt of twai1, level*/
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ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
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ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
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ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
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@@ -4,11 +4,6 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The long term plan is to have a single soc_caps.h for each peripheral.
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// During the refactoring and multichip support development process, we
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// seperate these information into periph_caps.h for each peripheral and
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// include them here.
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/*
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* These defines are parsed and imported as kconfig variables via the script
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* `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py`
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