esp_flash: fix set qe bit and write command issues

There used to be dummy phase before out phase in common command
transactions. This corrupts the data.

The code before never actually operate (clear) the QE bit, once it finds
the QE bit is set. It's hard to check whether the QE set/disable
functions work well.

This commit:

1. Cancel the dummy phase

2. Set and clear the QE bit according to chip settings, allowing tests
   for QE bits. However for some chips (Winbond for example), it's not
   forced to clear the QE bit if not able to.

3. Also refactor to allow chip_generic and other chips to share the same
   code to read and write qe bit; let common command and read command share
   configure_host_io_mode.

4. Rename read mode to io mode since maybe we will write data with quad
   mode one day.

components/spi_flash/include/spi_flash_chip_driver.h

@@ -149,7 +149,13 @@ struct spi_flash_chip_t {
      *
      * Can return ESP_ERR_FLASH_UNSUPPORTED_HOST or ESP_ERR_FLASH_UNSUPPORTED_CHIP if the specified mode is unsupported.
      */
-    esp_err_t (*set_read_mode)(esp_flash_t *chip);
+    esp_err_t (*set_io_mode)(esp_flash_t *chip);
+
+    /*
+     * Get whether the Quad Enable (QE) is set. (*out_io_mode)=SPI_FLASH_QOUT if
+     * enabled, otherwise disabled
+     */
+    esp_err_t (*get_io_mode)(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode);
 };
 
 /* Pointer to an array of pointers to all known drivers for flash chips. This array is used