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fix(wdt): bringup WDTs for CP MP

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This commit is contained in:
Marius Vikhammer
2024-06-28 09:51:57 +08:00
parent 8d34993193
commit 2ba6f989b7
8 changed files with 172 additions and 308 deletions
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150
components/hal/esp32c5/include/hal/lpwdt_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -68,9 +68,7 @@ ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Ad
*/
FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_en = 1;
abort();
hw->config0.wdt_en = 1;
}
/**
@@ -83,9 +81,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_en = 0;
abort();
hw->config0.wdt_en = 0;
}
/**
@@ -96,10 +92,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// return (hw->config0.wdt_en) ? true : false;
abort();
return (bool)0;
return (hw->config0.wdt_en) ? true : false;
}
/**
@@ -122,29 +115,27 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
*/
FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
{
// TODO: [ESP32C5] IDF-8635
// switch (stage) {
// case WDT_STAGE0:
// hw->config0.wdt_stg0 = behavior;
// //Account of implicty multiplier applied to stage 0 timeout tick config value
// hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
// break;
// case WDT_STAGE1:
// hw->config0.wdt_stg1 = behavior;
// hw->config2.val = timeout_ticks;
// break;
// case WDT_STAGE2:
// hw->config0.wdt_stg2 = behavior;
// hw->config3.val = timeout_ticks;
// break;
// case WDT_STAGE3:
// hw->config0.wdt_stg3 = behavior;
// hw->config4.val = timeout_ticks;
// break;
// default:
// abort();
// }
abort();
switch (stage) {
case WDT_STAGE0:
hw->config0.wdt_stg0 = behavior;
//Account of implicty multiplier applied to stage 0 timeout tick config value
hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
break;
case WDT_STAGE1:
hw->config0.wdt_stg1 = behavior;
hw->config2.val = timeout_ticks;
break;
case WDT_STAGE2:
hw->config0.wdt_stg2 = behavior;
hw->config3.val = timeout_ticks;
break;
case WDT_STAGE3:
hw->config0.wdt_stg3 = behavior;
hw->config4.val = timeout_ticks;
break;
default:
abort();
}
}
/**
@@ -155,24 +146,22 @@ FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage
*/
FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
{
// TODO: [ESP32C5] IDF-8635
// switch (stage) {
// case WDT_STAGE0:
// hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE1:
// hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE2:
// hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE3:
// hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
// break;
// default:
// abort();
// }
abort();
switch (stage) {
case WDT_STAGE0:
hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
break;
default:
abort();
}
}
/**
@@ -183,9 +172,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stag
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_cpu_reset_length = length;
abort();
hw->config0.wdt_cpu_reset_length = length;
}
/**
@@ -196,9 +183,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_sys_reset_length = length;
abort();
hw->config0.wdt_sys_reset_length = length;
}
/**
@@ -213,9 +198,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
abort();
hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
}
/**
@@ -226,9 +209,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
abort();
hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
}
/**
@@ -239,9 +220,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enabl
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
abort();
hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
}
/**
@@ -252,9 +231,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enabl
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
abort();
hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
}
/**
@@ -268,9 +245,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool ena
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635
// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
abort();
hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
}
/**
@@ -281,9 +256,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
{
// TODO: [ESP32C5] IDF-8635
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
abort();
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
}
/**
@@ -295,9 +268,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t
*/
FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// hw->feed.rtc_wdt_feed = 1;
abort();
hw->feed.rtc_wdt_feed = 1;
}
/**
@@ -307,9 +278,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
*/
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// hw->wprotect.val = 0;
abort();
hw->wprotect.val = 0;
}
/**
@@ -319,9 +288,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
*/
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// hw->wprotect.val = LP_WDT_WKEY_VALUE;
abort();
hw->wprotect.val = LP_WDT_WKEY_VALUE;
}
/**
@@ -332,9 +299,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
*/
FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8635
// hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
abort();
hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
}
/**
@@ -345,10 +310,7 @@ FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// return (hw->int_st.lp_wdt_int_st) ? true : false;
abort();
return (bool)0;
return (hw->int_st.lp_wdt_int_st) ? true : false;
}
/**
@@ -358,9 +320,7 @@ FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
*/
FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8635
// hw->int_clr.lp_wdt_int_clr = 1;
abort();
hw->int_clr.lp_wdt_int_clr = 1;
}
#ifdef __cplusplus

216
components/hal/esp32c5/include/hal/mwdt_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,7 +25,7 @@ extern "C" {
#include "hal/misc.h"
/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
#define MWDT_LL_DEFAULT_CLK_PRESCALER 20000
#define MWDT_LL_DEFAULT_CLK_PRESCALER 24000
/* Possible values for TIMG_WDT_STGx */
#define TIMG_WDT_STG_SEL_OFF 0
@@ -64,9 +64,7 @@ ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "
*/
FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtconfig0.wdt_en = 1;
abort();
hw->wdtconfig0.wdt_en = 1;
}
/**
@@ -79,9 +77,7 @@ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtconfig0.wdt_en = 0;
abort();
hw->wdtconfig0.wdt_en = 0;
}
/**
@@ -92,10 +88,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// return (hw->wdtconfig0.wdt_en) ? true : false;
abort();
return (bool)0;
return (hw->wdtconfig0.wdt_en) ? true : false;
}
/**
@@ -108,31 +101,29 @@ FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior)
{
// TODO: [ESP32C5] IDF-8650
// switch (stage) {
// case WDT_STAGE0:
// hw->wdtconfig0.wdt_stg0 = behavior;
// hw->wdtconfig2.wdt_stg0_hold = timeout;
// break;
// case WDT_STAGE1:
// hw->wdtconfig0.wdt_stg1 = behavior;
// hw->wdtconfig3.wdt_stg1_hold = timeout;
// break;
// case WDT_STAGE2:
// hw->wdtconfig0.wdt_stg2 = behavior;
// hw->wdtconfig4.wdt_stg2_hold = timeout;
// break;
// case WDT_STAGE3:
// hw->wdtconfig0.wdt_stg3 = behavior;
// hw->wdtconfig5.wdt_stg3_hold = timeout;
// break;
// default:
// HAL_ASSERT(false && "unsupported WDT stage");
// break;
// }
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
abort();
switch (stage) {
case WDT_STAGE0:
hw->wdtconfig0.wdt_stg0 = behavior;
hw->wdtconfig2.wdt_stg0_hold = timeout;
break;
case WDT_STAGE1:
hw->wdtconfig0.wdt_stg1 = behavior;
hw->wdtconfig3.wdt_stg1_hold = timeout;
break;
case WDT_STAGE2:
hw->wdtconfig0.wdt_stg2 = behavior;
hw->wdtconfig4.wdt_stg2_hold = timeout;
break;
case WDT_STAGE3:
hw->wdtconfig0.wdt_stg3 = behavior;
hw->wdtconfig5.wdt_stg3_hold = timeout;
break;
default:
HAL_ASSERT(false && "unsupported WDT stage");
break;
}
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@@ -143,27 +134,25 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u
*/
FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
{
// TODO: [ESP32C5] IDF-8650
// switch (stage) {
// case WDT_STAGE0:
// hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE1:
// hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE2:
// hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
// break;
// case WDT_STAGE3:
// hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
// break;
// default:
// HAL_ASSERT(false && "unsupported WDT stage");
// break;
// }
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
abort();
switch (stage) {
case WDT_STAGE0:
hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE1:
hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE2:
hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
break;
case WDT_STAGE3:
hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
break;
default:
HAL_ASSERT(false && "unsupported WDT stage");
break;
}
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@@ -174,11 +163,9 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtconfig0.wdt_cpu_reset_length = length;
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
abort();
hw->wdtconfig0.wdt_cpu_reset_length = length;
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@@ -189,11 +176,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtconfig0.wdt_sys_reset_length = length;
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
abort();
hw->wdtconfig0.wdt_sys_reset_length = length;
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@@ -208,11 +193,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_si
*/
FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
abort();
hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@@ -223,13 +206,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
{
// TODO: [ESP32C5] IDF-8650
// // In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
// // We take care of the "read-modify-write" procedure by ourselves.
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
// //Config registers are updated asynchronously
// hw->wdtconfig0.wdt_conf_update_en = 1;
abort();
// In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction (e.g. s8i, which is not allowed to access a register)
// We take care of the "read-modify-write" procedure by ourselves.
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescale, prescaler);
//Config registers are updated asynchronously
hw->wdtconfig0.wdt_conf_update_en = 1;
}
/**
@@ -241,9 +222,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
*/
FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtfeed.wdt_feed = 1;
abort();
hw->wdtfeed.wdt_feed = 1;
}
/**
@@ -255,9 +234,7 @@ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtwprotect.wdt_wkey = 0;
abort();
hw->wdtwprotect.wdt_wkey = 0;
}
/**
@@ -267,9 +244,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
abort();
hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
}
/**
@@ -279,9 +254,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
{
// TODO: [ESP32C5] IDF-8650
// hw->int_clr_timers.wdt_int_clr = 1;
abort();
hw->int_clr_timers.wdt_int_clr = 1;
}
/**
@@ -292,9 +265,7 @@ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
{
// TODO: [ESP32C5] IDF-8650
// hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
abort();
hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
}
/**
@@ -305,28 +276,27 @@ FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
*/
FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src)
{
// TODO: [ESP32C5] IDF-8650
// uint8_t clk_id = 0;
// switch (clk_src) {
// case MWDT_CLK_SRC_XTAL:
// clk_id = 0;
// break;
// case MWDT_CLK_SRC_PLL_F80M:
// clk_id = 1;
// break;
// case MWDT_CLK_SRC_RC_FAST:
// clk_id = 2;
// break;
// default:
// HAL_ASSERT(false);
// break;
// }
// // if (hw == &TIMERG0) {
// PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id;
// } else {
// PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id;
// }
abort();
uint8_t clk_id = 0;
switch (clk_src) {
case MWDT_CLK_SRC_XTAL:
clk_id = 0;
break;
case MWDT_CLK_SRC_PLL_F80M:
clk_id = 1;
break;
case MWDT_CLK_SRC_RC_FAST:
clk_id = 2;
break;
default:
HAL_ASSERT(false);
break;
}
if (hw == &TIMERG0) {
PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id;
} else {
PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id;
}
}
/**
@@ -338,13 +308,11 @@ FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_sourc
__attribute__((always_inline))
static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
{
// TODO: [ESP32C5] IDF-8650
// if (hw == &TIMERG0) {
// PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en;
// } else {
// PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
// }
abort();
if (hw == &TIMERG0) {
PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en;
} else {
PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
}
}