mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-09 12:35:28 +00:00
add gpio driver code
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@@ -27,7 +27,7 @@ typedef volatile struct {
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uint32_t enable: 1; /*When set timer 0/1 time-base counter is enabled*/
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};
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uint32_t val;
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}config;
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} config;
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uint32_t cnt_low; /*Register to store timer 0/1 time-base counter current value lower 32 bits.*/
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uint32_t cnt_high; /*Register to store timer 0 time-base counter current value higher 32 bits.*/
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uint32_t update; /*Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above)*/
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@@ -36,7 +36,7 @@ typedef volatile struct {
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uint32_t load_low; /*Lower 32 bits of the value that will load into timer 0 time-base counter*/
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uint32_t load_high; /*higher 32 bits of the value that will load into timer 0 time-base counter*/
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uint32_t reload; /*Write any value will trigger timer 0 time-base counter reload*/
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}hw_timer[2];
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} hw_timer[2];
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union {
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struct {
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uint32_t reserved0: 14;
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@@ -52,14 +52,14 @@ typedef volatile struct {
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uint32_t en: 1; /*When set SWDT is enabled*/
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};
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uint32_t val;
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}wdt_config0;
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} wdt_config0;
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union {
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struct {
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uint32_t reserved0: 16;
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uint32_t clk_prescale:16; /*SWDT clock prescale value. Period = 12.5ns * value stored in this register*/
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};
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uint32_t val;
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}wdt_config1;
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} wdt_config1;
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uint32_t wdt_config2; /*Stage 0 timeout value in SWDT clock cycles*/
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uint32_t wdt_config3; /*Stage 1 timeout value in SWDT clock cycles*/
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uint32_t wdt_config4; /*Stage 2 timeout value in SWDT clock cycles*/
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@@ -76,14 +76,14 @@ typedef volatile struct {
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uint32_t start: 1;
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};
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uint32_t val;
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}rtc_cali_cfg;
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} rtc_cali_cfg;
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union {
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struct {
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uint32_t reserved0: 7;
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uint32_t value:25;
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};
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uint32_t val;
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}rtc_cali_cfg1;
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} rtc_cali_cfg1;
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union {
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struct {
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uint32_t reserved0: 7;
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@@ -99,14 +99,14 @@ typedef volatile struct {
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uint32_t en: 1;
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};
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uint32_t val;
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}lactconfig;
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} lactconfig;
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union {
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struct {
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uint32_t reserved0: 6;
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uint32_t step_len:26;
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};
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uint32_t val;
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}lactrtc;
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} lactrtc;
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uint32_t lactlo; /**/
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uint32_t lacthi; /**/
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uint32_t lactupdate; /**/
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@@ -124,7 +124,7 @@ typedef volatile struct {
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uint32_t reserved4: 28;
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};
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uint32_t val;
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}int_ena;
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} int_ena;
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union {
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struct {
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uint32_t t0: 1; /*interrupt when timer0 alarm*/
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@@ -134,7 +134,7 @@ typedef volatile struct {
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uint32_t reserved4:28;
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};
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uint32_t val;
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}int_raw;
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} int_raw;
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union {
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struct {
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uint32_t t0: 1; /*interrupt when timer0 alarm*/
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@@ -144,7 +144,7 @@ typedef volatile struct {
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uint32_t reserved4: 28;
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};
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uint32_t val;
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}int_st_timers;
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} int_st_timers;
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union {
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struct {
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uint32_t t0: 1; /*interrupt when timer0 alarm*/
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@@ -154,7 +154,7 @@ typedef volatile struct {
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uint32_t reserved4: 28;
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};
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uint32_t val;
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}int_clr_timers;
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} int_clr_timers;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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@@ -181,14 +181,14 @@ typedef volatile struct {
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uint32_t reserved28: 4;
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};
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uint32_t val;
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}timg_date;
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} timg_date;
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union {
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struct {
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uint32_t reserved0: 31;
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uint32_t en: 1; /*Force clock enable for this regfile*/
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};
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uint32_t val;
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}clk;
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} clk;
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} timg_dev_t;
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extern timg_dev_t TIMERG0;
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extern timg_dev_t TIMERG1;
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