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clk_tree: Add basic clock support for esp32h2

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- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration

Remove FPGA build for esp32h2
This commit is contained in:
Song Ruo Jing
2023-02-09 15:39:38 +08:00
parent 89190fab02
commit 2c2a62e323
53 changed files with 3504 additions and 3611 deletions
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43
components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
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@@ -16,22 +16,6 @@
extern "C" {
#endif
/**
* @brief Reset (Disable) the I2C internal bus for all regi2c registers
*/
static inline void regi2c_ctrl_ll_i2c_reset(void)
{
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
}
/**
* @brief Enable the I2C internal bus to do I2C read/write operation to the BBPLL configuration register
*/
static inline void regi2c_ctrl_ll_i2c_bbpll_enable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_BBPLL_M);
}
/**
* @brief Start BBPLL self-calibration
*/
@@ -41,13 +25,32 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
}
/**
* @brief Stop BBPLL self-calibration
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
{
REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
}
/**
* @brief Check whether BBPLL calibration is done
*
* @return True if calibration is done; otherwise false
*/
static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
{
return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
}
/**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PD);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PU);
}
/**
@@ -55,8 +58,8 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
*/
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
CLEAR_PERI_REG_MASK(I2C_MST_ANA_CONF1_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(I2C_MST_ANA_CONF2_REG, ANA_I2C_SAR_FORCE_PD);
}
#ifdef __cplusplus