change(fpga): added bypass rng configuration

2025-09-18 15:53:53 +00:00 · 2023-12-05 10:42:19 +08:00
parent 4cd0a6a4b1
commit 2c32bd209a
19 changed files with 90 additions and 16 deletions
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -167,6 +167,10 @@ config SOC_SPI_FLASH_SUPPORTED
    bool
    default y

+config SOC_RNG_SUPPORTED
+    bool
+    default y
+
 config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
    int
    default 5
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -99,6 +99,7 @@
 #define SOC_MPU_SUPPORTED           1
 #define SOC_WDT_SUPPORTED           1
 #define SOC_SPI_FLASH_SUPPORTED     1
+#define SOC_RNG_SUPPORTED           1

 #if SOC_CAPS_ECO_VER < 200
 #define SOC_DPORT_WORKAROUND                   1