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Mark some interrupts that are now allocated dynamically as free, add int handle param documentation, add local ints test

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This commit is contained in:
Jeroen Domburg
2016-12-08 12:38:22 +08:00
parent 9dc908d105
commit 2c34ab3374
10 changed files with 154 additions and 124 deletions
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8
examples/13_timer_group/main/timer_group.c
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@@ -86,7 +86,9 @@ void IRAM_ATTR timer_group0_isr(void *para)
/*Timer0 is an example that don't reload counter value*/
TIMERG0.hw_timer[timer_idx].update = 1;
/*We don't call a API here because they are not declared with IRAM_ATTR*/
/* We don't call a API here because they are not declared with IRAM_ATTR.
If we're okay with the timer irq not being serviced while SPI flash cache is disabled,
we can alloc this interrupt without the ESP_INTR_FLAG_IRAM flag and use the normal API. */
TIMERG0.int_clr_timers.t0 = 1;
uint64_t timer_val = ((uint64_t) TIMERG0.hw_timer[timer_idx].cnt_high) << 32
| TIMERG0.hw_timer[timer_idx].cnt_low;
@@ -155,7 +157,7 @@ void tg0_timer0_init()
/*Enable timer interrupt*/
timer_enable_intr(timer_group, timer_idx);
/*Set ISR handler*/
timer_isr_register(timer_group, timer_idx, timer_group0_isr, (void*) timer_idx, 0);
timer_isr_register(timer_group, timer_idx, timer_group0_isr, (void*) timer_idx, ESP_INTR_FLAG_IRAM);
/*Start timer counter*/
timer_start(timer_group, timer_idx);
}
@@ -185,7 +187,7 @@ void tg0_timer1_init()
/*Enable timer interrupt*/
timer_enable_intr(timer_group, timer_idx);
/*Set ISR handler*/
timer_isr_register(timer_group, timer_idx, timer_group0_isr, (void*) timer_idx, 0);
timer_isr_register(timer_group, timer_idx, timer_group0_isr, (void*) timer_idx, ESP_INTR_FLAG_IRAM);
/*Start timer counter*/
timer_start(timer_group, timer_idx);
}