alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-10-08 22:01:42 +00:00
Code Issues Packages Projects Releases Wiki Activity

refactor(drivers): refactor the iram-safe option of the gdma peripherals

Browse Source 
Closes https://github.com/espressif/esp-idf/issues/15771
This commit is contained in:
morris
2025-04-14 18:19:36 +08:00
parent 7bcb7248bb
commit 2c376ff99f
22 changed files with 48 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/esp_driver_i2s/Kconfig
View File

@@ -3,7 +3,7 @@ menu "ESP-Driver:I2S Configurations"
config I2S_ISR_IRAM_SAFE
bool "I2S ISR IRAM-Safe"
default n
select GDMA_ISR_IRAM_SAFE if SOC_GDMA_SUPPORTED
select GDMA_ISR_HANDLER_IN_IRAM if SOC_GDMA_SUPPORTED
help
Ensure the I2S interrupt is IRAM-Safe by allowing the interrupt handler to be
executable when the cache is disabled (e.g. SPI Flash write).

6
components/esp_driver_i2s/i2s_common.c
View File

@@ -791,7 +791,11 @@ esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag)
}
/* Set GDMA config */
gdma_channel_alloc_config_t dma_cfg = {};
gdma_channel_alloc_config_t dma_cfg = {
#if CONFIG_I2S_ISR_IRAM_SAFE
.flags.isr_cache_safe = true,
#endif
};
if (handle->dir == I2S_DIR_TX) {
dma_cfg.direction = GDMA_CHANNEL_DIRECTION_TX;
/* Register a new GDMA tx channel */

2
components/esp_driver_i2s/i2s_private.h
View File

@@ -40,7 +40,7 @@ extern "C" {
// If ISR handler is allowed to run whilst cache is disabled,
// Make sure all the code and related variables used by the handler are in the SRAM
#if CONFIG_I2S_ISR_IRAM_SAFE || CONFIG_GDMA_ISR_IRAM_SAFE
#if CONFIG_I2S_ISR_IRAM_SAFE
#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED)
#define I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else