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fix(ci): bypass c5mp ci check

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This commit is contained in:
Lou Tianhao
2024-04-07 17:17:24 +08:00
committed by wuzhenghui
parent 22c66db66b
commit 2c59c4fbf2
9 changed files with 184 additions and 17 deletions
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40
components/hal/esp32c5/include/hal/lp_timer_ll.h
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@@ -13,6 +13,7 @@
#include "soc/rtc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_aon_reg.h"
#include "hal/assert.h"
#include "hal/lp_timer_types.h"
#include "esp_attr.h"
@@ -31,8 +32,12 @@ extern "C" {
*/
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->target[timer_id].hi.main_timer_tar_high = (value >> 32) & 0xFFFF;
dev->target[timer_id].lo.main_timer_tar_low = value & 0xFFFFFFFF;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@@ -46,7 +51,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t
*/
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->target[timer_id].hi.main_timer_tar_en = en;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@@ -59,7 +68,12 @@ FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_
*/
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->counter[buffer_id].lo.main_timer_buf_low;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
return 0;
#endif
}
/**
@@ -72,7 +86,12 @@ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev
*/
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
return dev->counter[buffer_id].hi.main_timer_buf_high;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
return 0;
#endif
}
/**
@@ -84,7 +103,11 @@ FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *de
*/
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->update.main_timer_update = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@@ -96,7 +119,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
*/
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_clr.soc_wakeup_int_clr = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@@ -108,7 +135,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
*/
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->int_clr.overflow_clr = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@@ -120,7 +151,11 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *de
*/
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
dev->lp_int_clr.main_timer_lp_int_clr = 1;
#else
HAL_ASSERT(false && "lp_timer not supported yet");
#endif
}
/**
@@ -132,8 +167,13 @@ FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *de
*/
FORCE_INLINE_ATTR uint64_t lp_timer_ll_time_to_count(uint64_t time_in_us)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t slow_clk_value = REG_READ(LP_AON_STORE1_REG);
return ((time_in_us * (1 << RTC_CLK_CAL_FRACT)) / slow_clk_value);
#else
HAL_ASSERT(false && "lp_timer not supported yet");
return 0;
#endif
}
#ifdef __cplusplus