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feat(gpio): add gpio support on ESP32C5 MP version

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This commit is contained in:
gaoxu
2024-05-16 14:54:27 +08:00
parent ea010f84ef
commit 2cad39aee5
19 changed files with 287 additions and 4351 deletions
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22
components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
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@@ -34,7 +34,7 @@ typedef union {
uint32_t reserved_15:17;
};
uint32_t val;
} iomux_pin_ctrl_reg_t;
} io_mux_pin_ctrl_reg_t;
/** Type of gpio register
* IO MUX Configure Register for pad XTAL_32K_P
@@ -102,13 +102,13 @@ typedef union {
uint32_t hys_en:1;
/** hys_sel : R/W; bitpos: [17]; default: 0;
* Select enabling signals of the pad from software and efuse hardware. 1: Select
* enabling siganl from slftware. 0: Select enabling signal from efuse hardware.
* enabling signal from slftware. 0: Select enabling signal from efuse hardware.
*/
uint32_t hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} iomux_gpio_reg_t;
} io_mux_gpio_reg_t;
/** Type of date register
* IO MUX Version Control Register
@@ -122,20 +122,20 @@ typedef union {
uint32_t reserved_28:4;
};
uint32_t val;
} iomux_date_reg_t;
} io_mux_date_reg_t;
typedef struct iomux_dev_t {
volatile iomux_pin_ctrl_reg_t pin_ctrl;
volatile iomux_gpio_reg_t gpio[27];
typedef struct io_mux_dev_t {
volatile io_mux_pin_ctrl_reg_t pin_ctrl;
volatile io_mux_gpio_reg_t gpio[27];
uint32_t reserved_070[35];
volatile iomux_date_reg_t date;
} iomux_dev_t;
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern iomux_dev_t IOMUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(iomux_dev_t) == 0x100, "Invalid size of iomux_dev_t structure");
_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
#endif
#ifdef __cplusplus

2
components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
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@@ -41,7 +41,7 @@ PROVIDE ( DS = 0x6008C000 );
PROVIDE ( HMAC = 0x6008D000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( IOMUX = 0x60090000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091f00 );
PROVIDE ( SDM = 0x60091f00 );

28
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
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@@ -111,17 +111,41 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
bool
default y
config SOC_GPIO_PORT
int
default 1
config SOC_GPIO_PIN_COUNT
int
default 29
config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 30
default 28
config SOC_GPIO_OUT_RANGE_MAX
int
default 30
default 28
config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
int
default 0
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x0000000001FFFF00
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
default y
config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
bool

4216
components/soc/esp32c5/mp/include/soc/io_mux_reg.h
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File diff suppressed because it is too large Load Diff

2
components/soc/esp32c5/mp/include/soc/io_mux_struct.h
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@@ -134,7 +134,7 @@ typedef struct {
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IOMUX;
extern io_mux_dev_t IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");

20
components/soc/esp32c5/mp/include/soc/soc_caps.h
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@@ -174,35 +174,35 @@
// #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
/*-------------------------- GPIO CAPS ---------------------------------------*/
// TODO: [ESP32C5] IDF-8717
// ESP32-C5 has 1 GPIO peripheral
// #define SOC_GPIO_PORT 1U
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 29
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1
// Target has the full LP IO subsystem
// On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) // TODO: [ESP32C5] IDF-8719
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 30
#define SOC_GPIO_OUT_RANGE_MAX 30
#define SOC_GPIO_IN_RANGE_MAX 28
#define SOC_GPIO_OUT_RANGE_MAX 28
// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
// #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL
// Support to force hold all IOs
// #define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
// Support to hold a single digital I/O when the digital domain is powered off
#define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1)

2
components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
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@@ -39,7 +39,7 @@ PROVIDE ( ECC = 0x6008B000 );
PROVIDE ( DS = 0x6008C000 );
PROVIDE ( HMAC = 0x6008D000 );
PROVIDE ( ECDSA = 0x6008E000 );
PROVIDE ( IOMUX = 0x60090000 );
PROVIDE ( IO_MUX = 0x60090000 );
PROVIDE ( GPIO = 0x60091000 );
PROVIDE ( GPIO_EXT = 0x60091f00 );
PROVIDE ( MEM_MONITOR = 0x60092000 );