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refactor(regi2c): ana i2c master clock is enabled per request

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This commit is contained in:
Song Ruo Jing
2024-08-07 21:04:36 +08:00
parent 92ed77933b
commit 2cb35a2955
55 changed files with 334 additions and 175 deletions
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26
components/esp_hw_support/port/esp32c5/rtc_clk.c
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@@ -22,10 +22,7 @@
#include "esp_private/sleep_event.h"
#include "hal/efuse_hal.h"
#include "soc/chip_revision.h"
#if SOC_MODEM_CLOCK_SUPPORTED
#include "esp_private/esp_modem_clock.h"
#endif
#include "esp_private/regi2c_ctrl.h"
static const char *TAG = "rtc_clk";
@@ -133,27 +130,13 @@ static void rtc_clk_bbpll_enable(void)
clk_ll_bbpll_enable();
}
static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
{
#if SOC_MODEM_CLOCK_SUPPORTED
#ifdef BOOTLOADER_BUILD
regi2c_ctrl_ll_master_enable_clock(enable);
#else
if (enable) {
modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
} else {
modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
}
#endif
#endif
}
static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
{
/* Digital part */
clk_ll_bbpll_set_freq_mhz(pll_freq);
/* Analog part */
rtc_clk_enable_i2c_ana_master_clock(true);
ANALOG_CLOCK_ENABLE();
/* BBPLL CALIBRATION START */
regi2c_ctrl_ll_bbpll_calibration_start();
clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -162,7 +145,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
esp_rom_delay_us(10); // wait for true stop
/* BBPLL CALIBRATION STOP */
regi2c_ctrl_ll_bbpll_calibration_stop();
rtc_clk_enable_i2c_ana_master_clock(false);
ANALOG_CLOCK_DISABLE();
s_cur_pll_freq = pll_freq;
}

1
components/esp_hw_support/port/esp32c5/rtc_clk_init.c
View File

@@ -79,6 +79,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
uint32_t hp_cali_dbias = get_act_hp_dbias();
uint32_t lp_cali_dbias = get_act_lp_dbias();