mirror of
https://github.com/espressif/esp-idf.git
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change(esp_rom): optimize target-specific header files layout in components/esp_rom
This commit is contained in:
Xiaoyu Liu
49
components/esp_rom/esp32/include/esp32/rom/aes.h
Normal file
49
components/esp_rom/esp32/include/esp32/rom/aes.h
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@@ -0,0 +1,49 @@
|
||||
/*
|
||||
ROM functions for hardware AES support.
|
||||
|
||||
It is not recommended to use these functions directly,
|
||||
use the wrapper functions in esp32/aes.h instead.
|
||||
|
||||
*/
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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||||
* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_AES_H_
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#define _ROM_AES_H_
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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//TODO, add comment for aes apis
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enum AES_BITS {
|
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AES128,
|
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AES192,
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AES256
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};
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void ets_aes_enable(void);
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void ets_aes_disable(void);
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void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
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bool in_word_swap, bool in_byte_swap,
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bool out_word_swap, bool out_byte_swap);
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||||
|
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bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);
|
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|
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bool ets_aes_setkey_dec(const uint8_t *key, enum AES_BITS bits);
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||||
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||||
void ets_aes_crypt(const uint8_t input[16], uint8_t output[16]);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_AES_H_ */
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54
components/esp_rom/esp32/include/esp32/rom/bigint.h
Normal file
54
components/esp_rom/esp32/include/esp32/rom/bigint.h
Normal file
@@ -0,0 +1,54 @@
|
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/*
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ROM functions for hardware bigint support.
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|
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It is not recommended to use these functions directly,
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use the wrapper functions in hwcrypto/mpi.h instead.
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|
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*/
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/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_BIGINT_H_
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#define _ROM_BIGINT_H_
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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//TODO: add comment here
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void ets_bigint_enable(void);
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void ets_bigint_disable(void);
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void ets_bigint_wait_finish(void);
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bool ets_bigint_mod_power_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
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uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
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bool ets_bigint_mod_power_getz(uint32_t *z, uint32_t len);
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bool ets_bigint_mult_prepare(uint32_t *x, uint32_t *y, uint32_t len);
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bool ets_bigint_mult_getz(uint32_t *z, uint32_t len);
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bool ets_bigint_montgomery_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
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uint32_t m_dash, uint32_t len, bool again);
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bool ets_bigint_montgomery_mult_getz(uint32_t *z, uint32_t len);
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bool ets_bigint_mod_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
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uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
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bool ets_bigint_mod_mult_getz(uint32_t *m, uint32_t *z, uint32_t len);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_BIGINT_H_ */
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185
components/esp_rom/esp32/include/esp32/rom/cache.h
Normal file
185
components/esp_rom/esp32/include/esp32/rom/cache.h
Normal file
@@ -0,0 +1,185 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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||||
*
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||||
* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ROM_CACHE_H_
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#define _ROM_CACHE_H_
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#include "esp_attr.h"
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#if __has_include("dport_access.h")
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#include "dport_access.h"
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#else
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#pragma message("For ESP32 with ECO version < 2, you need to use a DPORT workaround that stalls the other CPU")
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#define DPORT_STALL_OTHER_CPU_START()
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#define DPORT_STALL_OTHER_CPU_END()
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup uart_apis, uart configuration and communication related apis
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* @brief uart apis
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*/
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/** @addtogroup uart_apis
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* @{
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*/
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/**
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* @brief Initialise cache mmu, mark all entries as invalid.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
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*
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* @return None
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||||
*/
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void mmu_init(int cpu_no);
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/**
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* @brief Set Flash-Cache mmu mapping.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
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*
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* @param int pod : process identifier. Range 0~7.
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*
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* @param unsigned int vaddr : virtual address in CPU address space.
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* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
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* Should be aligned by psize.
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*
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* @param unsigned int paddr : physical address in Flash.
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* Should be aligned by psize.
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*
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* @param int psize : page size of flash, in kilobytes. Should be 64 here.
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*
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* @param int num : pages to be set.
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*
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* @return unsigned int: error status
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* 0 : mmu set success
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* 1 : vaddr or paddr is not aligned
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* 2 : pid error
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* 3 : psize error
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||||
* 4 : mmu table to be written is out of range
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* 5 : vaddr is out of range
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*/
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static inline __attribute__((always_inline)) unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
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{
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extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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unsigned int ret;
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DPORT_STALL_OTHER_CPU_START();
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ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
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DPORT_STALL_OTHER_CPU_END();
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return ret;
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}
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/**
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* @brief Set Ext-SRAM-Cache mmu mapping.
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* Please do not call this function in your SDK application.
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*
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* Note that this code lives in IRAM and has a bugfix in respect to the ROM version
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||||
* of this function (which erroneously refused a vaddr > 2MiB
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*
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* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
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||||
*
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||||
* @param int pod : process identifier. Range 0~7.
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||||
*
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||||
* @param unsigned int vaddr : virtual address in CPU address space.
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||||
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
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||||
* Should be aligned by psize.
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||||
*
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||||
* @param unsigned int paddr : physical address in Ext-SRAM.
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||||
* Should be aligned by psize.
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||||
*
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||||
* @param int psize : page size of flash, in kilobytes. Should be 32 here.
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||||
*
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||||
* @param int num : pages to be set.
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||||
*
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||||
* @return unsigned int: error status
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||||
* 0 : mmu set success
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||||
* 1 : vaddr or paddr is not aligned
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||||
* 2 : pid error
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* 3 : psize error
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||||
* 4 : mmu table to be written is out of range
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* 5 : vaddr is out of range
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*/
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unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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/**
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* @brief Initialise cache access for the cpu.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
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||||
*
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||||
* @return None
|
||||
*/
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||||
static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Init(int cpu_no)
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{
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extern void Cache_Read_Init_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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||||
Cache_Read_Init_rom(cpu_no);
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||||
DPORT_STALL_OTHER_CPU_END();
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||||
}
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||||
|
||||
/**
|
||||
* @brief Flush the cache value for the cpu.
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* Please do not call this function in your SDK application.
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||||
*
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||||
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
|
||||
*
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||||
* @return None
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||||
*/
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static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Flush(int cpu_no)
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||||
{
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extern void Cache_Flush_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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Cache_Flush_rom(cpu_no);
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DPORT_STALL_OTHER_CPU_END();
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}
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|
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/**
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||||
* @brief Disable Cache access for the cpu.
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||||
* Please do not call this function in your SDK application.
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||||
*
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||||
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
|
||||
*
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||||
* @return None
|
||||
*/
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||||
static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Disable(int cpu_no)
|
||||
{
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||||
extern void Cache_Read_Disable_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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Cache_Read_Disable_rom(cpu_no);
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DPORT_STALL_OTHER_CPU_END();
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}
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||||
|
||||
/**
|
||||
* @brief Enable Cache access for the cpu.
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||||
* Please do not call this function in your SDK application.
|
||||
*
|
||||
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
|
||||
*
|
||||
* @return None
|
||||
*/
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||||
static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Enable(int cpu_no)
|
||||
{
|
||||
extern void Cache_Read_Enable_rom(int cpu_no);
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DPORT_STALL_OTHER_CPU_START();
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Cache_Read_Enable_rom(cpu_no);
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||||
DPORT_STALL_OTHER_CPU_END();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
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||||
#ifdef __cplusplus
|
||||
}
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||||
#endif
|
||||
|
||||
#endif /* _ROM_CACHE_H_ */
|
||||
152
components/esp_rom/esp32/include/esp32/rom/crc.h
Normal file
152
components/esp_rom/esp32/include/esp32/rom/crc.h
Normal file
@@ -0,0 +1,152 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ROM_CRC_H
|
||||
#define ROM_CRC_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup uart_apis, uart configuration and communication related apis
|
||||
* @brief uart apis
|
||||
*/
|
||||
|
||||
/** @addtogroup uart_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Notes about CRC APIs usage
|
||||
* The ESP32 ROM include some CRC tables and CRC APIs to speed up CRC calculation.
|
||||
* The CRC APIs include CRC8, CRC16, CRC32 algorithms for both little endian and big endian modes.
|
||||
* Here are the polynomials for the algorithms:
|
||||
* CRC-8 x8+x2+x1+1 0x07
|
||||
* CRC16-CCITT x16+x12+x5+1 0x1021
|
||||
* CRC32 x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1 0x04c11db7
|
||||
*
|
||||
* These group of CRC APIs are designed to calculate the data in buffers either continuous or not.
|
||||
* To make it easy, we had added a `~` at the beginning and the end of the functions.
|
||||
* To calculate non-continuous buffers, we can write the code like this:
|
||||
* init = ~init;
|
||||
* crc = crc32_le(init, buf0, length0);
|
||||
* crc = crc32_le(crc, buf1, length1);
|
||||
* crc = ~crc;
|
||||
*
|
||||
* However, it is not easy to select which API to use and give the correct parameters.
|
||||
* A specific CRC algorithm will include this parameters: width, polynomials, init, refin, refout, xorout
|
||||
* refin and refout show the endian of the algorithm:
|
||||
* if both of them are true, please use the little endian API.
|
||||
* if both of them are false, please use the big endian API.
|
||||
* xorout is the value which you need to be xored to the raw result.
|
||||
* However, these group of APIs need one '~' before and after the APIs.
|
||||
*
|
||||
* Here are some examples for CRC16:
|
||||
* CRC-16/CCITT, poly = 0x1021, init = 0x0000, refin = true, refout = true, xorout = 0x0000
|
||||
* crc = ~crc16_le((uint16_t)~0x0000, buf, length);
|
||||
*
|
||||
* CRC-16/CCITT-FALSE, poly = 0x1021, init = 0xffff, refin = false, refout = false, xorout = 0x0000
|
||||
* crc = ~crc16_be((uint16_t)~0xffff, buf, length);
|
||||
*
|
||||
* CRC-16/X25, poly = 0x1021, init = 0xffff, refin = true, refout = true, xorout = 0xffff
|
||||
* crc = (~crc16_le((uint16_t)~(0xffff), buf, length))^0xffff;
|
||||
*
|
||||
* CRC-16/XMODEM, poly= 0x1021, init = 0x0000, refin = false, refout = false, xorout = 0x0000
|
||||
* crc = ~crc16_be((uint16_t)~0x0000, buf, length);
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC32 value that is in little endian.
|
||||
*
|
||||
* @param uint32_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief CRC32 value that is in big endian.
|
||||
*
|
||||
* @param uint32_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief CRC16 value that is in little endian.
|
||||
*
|
||||
* @param uint16_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief CRC16 value that is in big endian.
|
||||
*
|
||||
* @param uint16_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief CRC8 value that is in little endian.
|
||||
*
|
||||
* @param uint8_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief CRC8 value that is in big endian.
|
||||
*
|
||||
* @param uint32_t crc : init crc value, use 0 at the first use.
|
||||
*
|
||||
* @param uint8_t const *buf : buffer to start calculate crc.
|
||||
*
|
||||
* @param uint32_t len : buffer length in byte.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
110
components/esp_rom/esp32/include/esp32/rom/efuse.h
Normal file
110
components/esp_rom/esp32/include/esp32/rom/efuse.h
Normal file
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _ROM_EFUSE_H_
|
||||
#define _ROM_EFUSE_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup efuse_APIs efuse APIs
|
||||
* @brief ESP32 efuse read/write APIs
|
||||
* @attention
|
||||
*
|
||||
*/
|
||||
|
||||
/** @addtogroup efuse_APIs
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Do a efuse read operation, to update the efuse value to efuse read registers.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void ets_efuse_read_op(void);
|
||||
|
||||
/**
|
||||
* @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return null
|
||||
*/
|
||||
void ets_efuse_program_op(void);
|
||||
|
||||
/**
|
||||
* @brief Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
|
||||
* It can be used to test the external xtal frequency, do not touch this efuse field.
|
||||
*
|
||||
* @param null
|
||||
*
|
||||
* @return u32: 1 for 100KHZ, range is 0 to 255.
|
||||
*/
|
||||
uint32_t ets_efuse_get_8M_clock(void);
|
||||
|
||||
/**
|
||||
* @brief Read spi flash pin configuration from Efuse
|
||||
*
|
||||
* @return
|
||||
* - 0 for default SPI pins.
|
||||
* - 1 for default HSPI pins.
|
||||
* - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
|
||||
* EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
|
||||
* WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
|
||||
*/
|
||||
uint32_t ets_efuse_get_spiconfig(void);
|
||||
|
||||
#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
|
||||
#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
|
||||
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
|
||||
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
|
||||
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
|
||||
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
|
||||
|
||||
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
|
||||
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
|
||||
|
||||
/**
|
||||
* @brief A crc8 algorithm used in efuse check.
|
||||
*
|
||||
* @param unsigned char const *p : Pointer to original data.
|
||||
*
|
||||
* @param unsigned int len : Data length in byte.
|
||||
*
|
||||
* @return unsigned char: Crc value.
|
||||
*/
|
||||
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_EFUSE_H_ */
|
||||
644
components/esp_rom/esp32/include/esp32/rom/ets_sys.h
Normal file
644
components/esp_rom/esp32/include/esp32/rom/ets_sys.h
Normal file
@@ -0,0 +1,644 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifndef CONFIG_IDF_TARGET_ESP32
|
||||
#error "This header should only be included when building for ESP32"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup ets_sys_apis, ets system related apis
|
||||
* @brief ets system apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_sys_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* NOTE
|
||||
* Many functions in this header files can't be run in FreeRTOS.
|
||||
* Please see the comment of the Functions.
|
||||
* There are also some functions that doesn't work on FreeRTOS
|
||||
* without listed in the header, such as:
|
||||
* xtos functions start with "_xtos_" in ld file.
|
||||
*
|
||||
***********************************************************************
|
||||
*/
|
||||
|
||||
/** \defgroup ets_apis, Espressif Task Scheduler related apis
|
||||
* @brief ets apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
ETS_OK = 0, /**< return successful in ets*/
|
||||
ETS_FAILED = 1, /**< return failed in ets*/
|
||||
ETS_PENDING = 2,
|
||||
ETS_BUSY = 3,
|
||||
ETS_CANCEL = 4,
|
||||
} ETS_STATUS;
|
||||
|
||||
typedef uint32_t ETSSignal;
|
||||
typedef uint32_t ETSParam;
|
||||
|
||||
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
|
||||
|
||||
struct ETSEventTag {
|
||||
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
|
||||
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
|
||||
};
|
||||
|
||||
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processor*/
|
||||
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
|
||||
|
||||
/**
|
||||
* @brief Start the Espressif Task Scheduler, which is an infinite loop. Please do not add code after it.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void ets_run(void);
|
||||
|
||||
/**
|
||||
* @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
|
||||
*
|
||||
* @param ets_idle_cb_t func : The callback function.
|
||||
*
|
||||
* @param void *arg : Argument of the callback.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Init a task with processor, priority, queue to receive Event, queue length.
|
||||
*
|
||||
* @param ETSTask task : The task processor.
|
||||
*
|
||||
* @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
|
||||
*
|
||||
* @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
|
||||
*
|
||||
* @param uint8_t qlen : Queue length.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
|
||||
|
||||
/**
|
||||
* @brief Post an event to an Task.
|
||||
*
|
||||
* @param uint8_t prio : Priority of the Task.
|
||||
*
|
||||
* @param ETSSignal sig : Event signal.
|
||||
*
|
||||
* @param ETSParam par : Event parameter
|
||||
*
|
||||
* @return ETS_OK : post successful
|
||||
* @return ETS_FAILED : post failed
|
||||
*/
|
||||
ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_boot_apis, Boot routing related apis
|
||||
* @brief ets boot apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern const char *const exc_cause_table[40]; ///**< exception cause that defined by the core.*/
|
||||
|
||||
/**
|
||||
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
|
||||
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
|
||||
*
|
||||
* @param uint32_t start : the PRO Entry code address value in uint32_t
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_set_user_start(uint32_t start);
|
||||
|
||||
/**
|
||||
* @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code.
|
||||
* When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run.
|
||||
*
|
||||
* @param uint32_t callback : the Startup code address value in uint32_t
|
||||
*
|
||||
* @return None : post successful
|
||||
*/
|
||||
void ets_set_startup_callback(uint32_t callback);
|
||||
|
||||
/**
|
||||
* @brief Set App cpu Entry code, code can be called in PRO CPU.
|
||||
* When APP booting is completed, APP CPU will call the Entry code if not NULL.
|
||||
*
|
||||
* @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_set_appcpu_boot_addr(uint32_t start);
|
||||
|
||||
/**
|
||||
* @brief unpack the image in flash to iram and dram, no using cache.
|
||||
*
|
||||
* @param uint32_t pos : Flash physical address.
|
||||
*
|
||||
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
|
||||
*
|
||||
* @param bool jump : Jump into the code in the function or not.
|
||||
*
|
||||
* @param bool config : Config the flash when unpacking the image, config should be done only once.
|
||||
*
|
||||
* @return ETS_OK : unpack successful
|
||||
* @return ETS_FAILED : unpack failed
|
||||
*/
|
||||
ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config);
|
||||
|
||||
/**
|
||||
* @brief unpack the image in flash to iram and dram, using cache, maybe decrypting.
|
||||
*
|
||||
* @param uint32_t pos : Flash physical address.
|
||||
*
|
||||
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
|
||||
*
|
||||
* @param bool jump : Jump into the code in the function or not.
|
||||
*
|
||||
* @param bool sb_need_check : Do security boot check or not.
|
||||
*
|
||||
* @param bool config : Config the flash when unpacking the image, config should be done only once.
|
||||
*
|
||||
* @return ETS_OK : unpack successful
|
||||
* @return ETS_FAILED : unpack failed
|
||||
*/
|
||||
ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
|
||||
* @brief ets printf apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_printf_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
|
||||
* Can not print float point data format, or longlong data format.
|
||||
* So we maybe only use this in ROM.
|
||||
*
|
||||
* @param const char *fmt : See printf.
|
||||
*
|
||||
* @param ... : See printf.
|
||||
*
|
||||
* @return int : the length printed to the output device.
|
||||
*/
|
||||
int ets_printf(const char *fmt, ...);
|
||||
|
||||
/**
|
||||
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
|
||||
* Can not print float point data format, or longlong data format
|
||||
*
|
||||
* @param char c : char to output.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_write_char_uart(char c);
|
||||
|
||||
/**
|
||||
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
|
||||
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
|
||||
*
|
||||
* @param void (*)(char) p: Output function to install.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_putc1(void (*p)(char c));
|
||||
|
||||
/**
|
||||
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
|
||||
* To install putc2, which is defaulted installed as NULL.
|
||||
*
|
||||
* @param void (*)(char) p: Output function to install.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_putc2(void (*p)(char c));
|
||||
|
||||
/**
|
||||
* @brief Install putc1 as ets_write_char_uart.
|
||||
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_install_uart_printf(void);
|
||||
|
||||
#define ETS_PRINTF(...) ets_printf(...)
|
||||
|
||||
#define ETS_ASSERT(v) do { \
|
||||
if (!(v)) { \
|
||||
ets_printf("%s %u \n", __FILE__, __LINE__); \
|
||||
while (1) {}; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
|
||||
* @brief ets timer apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_timer_apis
|
||||
* @{
|
||||
*/
|
||||
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
|
||||
|
||||
typedef struct _ETSTIMER_ {
|
||||
struct _ETSTIMER_ *timer_next; /**< timer linker*/
|
||||
uint32_t timer_expire; /**< abstract time when timer expire*/
|
||||
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
|
||||
ETSTimerFunc *timer_func; /**< timer handler*/
|
||||
void *timer_arg; /**< timer handler argument*/
|
||||
} ETSTimer;
|
||||
|
||||
/**
|
||||
* @brief Init ets timer, this timer range is 640 us to 429496 ms
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_init(void);
|
||||
|
||||
/**
|
||||
* @brief In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_deinit(void);
|
||||
|
||||
/**
|
||||
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
|
||||
*
|
||||
* @param bool repeat : Timer is periodic repeated.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
|
||||
|
||||
/**
|
||||
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
|
||||
*
|
||||
* @param bool repeat : Timer is periodic repeated.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
|
||||
|
||||
/**
|
||||
* @brief Disarm an ets timer.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_disarm(ETSTimer *timer);
|
||||
|
||||
/**
|
||||
* @brief Set timer callback and argument.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @param ETSTimerFunc *pfunction : Timer callback.
|
||||
*
|
||||
* @param void *parg : Timer callback argument.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
|
||||
|
||||
/**
|
||||
* @brief Unset timer callback and argument to NULL.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param ETSTimer *timer : Timer struct pointer.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_timer_done(ETSTimer *ptimer);
|
||||
|
||||
/**
|
||||
* @brief CPU do while loop for some time.
|
||||
* In FreeRTOS task, please call FreeRTOS apis.
|
||||
*
|
||||
* @param uint32_t us : Delay time in us.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_delay_us(uint32_t us);
|
||||
|
||||
/**
|
||||
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
|
||||
* Call this function when CPU frequency is changed.
|
||||
*
|
||||
* @param uint32_t ticks_per_us : CPU ticks per us.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_update_cpu_frequency(uint32_t ticks_per_us);
|
||||
|
||||
/**
|
||||
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
|
||||
*
|
||||
* @note This function only sets the tick rate for the current CPU. It is located in ROM,
|
||||
* so the deep sleep stub can use it even if IRAM is not initialized yet.
|
||||
*
|
||||
* @param uint32_t ticks_per_us : CPU ticks per us.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
|
||||
|
||||
/**
|
||||
* @brief Get the real CPU ticks per us to the ets.
|
||||
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : CPU ticks per us record in ets.
|
||||
*/
|
||||
uint32_t ets_get_cpu_frequency(void);
|
||||
|
||||
/**
|
||||
* @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : xtal_freq/analog_8M*256.
|
||||
*/
|
||||
uint32_t ets_get_xtal_scale(void);
|
||||
|
||||
/**
|
||||
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
|
||||
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
|
||||
* else if analog_8M in efuse
|
||||
* clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
|
||||
* else clock = 26M.
|
||||
*/
|
||||
uint32_t ets_get_detected_xtal_freq(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** \defgroup ets_intr_apis, ets interrupt configure related apis
|
||||
* @brief ets intr apis
|
||||
*/
|
||||
|
||||
/** @addtogroup ets_intr_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
|
||||
|
||||
/**
|
||||
* @brief Attach a interrupt handler to a CPU interrupt number.
|
||||
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param int i : CPU interrupt number.
|
||||
*
|
||||
* @param ets_isr_t func : Interrupt handler.
|
||||
*
|
||||
* @param void *arg : argument of the handler.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_attach(int i, ets_isr_t func, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Mask the interrupts which show in mask bits.
|
||||
* This function equals to _xtos_ints_off(mask).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_mask(uint32_t mask);
|
||||
|
||||
/**
|
||||
* @brief Unmask the interrupts which show in mask bits.
|
||||
* This function equals to _xtos_ints_on(mask).
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_isr_unmask(uint32_t unmask);
|
||||
|
||||
/**
|
||||
* @brief Lock the interrupt to level 2.
|
||||
* This function direct set the CPU registers.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_intr_lock(void);
|
||||
|
||||
/**
|
||||
* @brief Unlock the interrupt to level 0.
|
||||
* This function direct set the CPU registers.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_intr_unlock(void);
|
||||
|
||||
/**
|
||||
* @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
|
||||
* This function direct set the CPU registers.
|
||||
* In FreeRTOS, please call FreeRTOS apis, never call this api.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ets_waiti0(void);
|
||||
|
||||
/**
|
||||
* @brief Attach an CPU interrupt to a hardware source.
|
||||
* We have 4 steps to use an interrupt:
|
||||
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
|
||||
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
|
||||
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
|
||||
* 4.Enable interrupt in the module.
|
||||
*
|
||||
* @param int cpu_no : The CPU which the interrupt number belongs.
|
||||
*
|
||||
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
|
||||
*
|
||||
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
|
||||
|
||||
#define _ETSTR(v) # v
|
||||
#define _ETS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \
|
||||
__asm__ __volatile__( "rsil %0, " _ETSTR(intlevel) "\n" \
|
||||
: "=a" (__tmp) : : "memory" ); \
|
||||
})
|
||||
|
||||
#ifdef CONFIG_NONE_OS
|
||||
#define ETS_INTR_LOCK() \
|
||||
ets_intr_lock()
|
||||
|
||||
#define ETS_INTR_UNLOCK() \
|
||||
ets_intr_unlock()
|
||||
|
||||
#define ETS_ISR_ATTACH \
|
||||
ets_isr_attach
|
||||
|
||||
#define ETS_INTR_ENABLE(inum) \
|
||||
ets_isr_unmask((1<<inum))
|
||||
|
||||
#define ETS_INTR_DISABLE(inum) \
|
||||
ets_isr_mask((1<<inum))
|
||||
|
||||
#define ETS_WMAC_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_WMAC_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_GPIO_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_UART0_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_UART0_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_WDT_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_SLC_INTR_ATTACH(func, arg) \
|
||||
ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
|
||||
|
||||
#define ETS_BB_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_BB_INUM)
|
||||
|
||||
#define ETS_BB_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_BB_INUM)
|
||||
|
||||
#define ETS_UART0_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_UART0_INUM)
|
||||
|
||||
#define ETS_UART0_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_UART0_INUM)
|
||||
|
||||
#define ETS_GPIO_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_GPIO_INUM)
|
||||
|
||||
#define ETS_GPIO_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_GPIO_INUM)
|
||||
|
||||
#define ETS_WDT_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_WDT_INUM)
|
||||
|
||||
#define ETS_WDT_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_WDT_INUM)
|
||||
|
||||
#define ETS_TG0_T0_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_TG0_T0_INUM)
|
||||
|
||||
#define ETS_TG0_T0_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_TG0_T0_INUM)
|
||||
|
||||
#define ETS_SLC_INTR_ENABLE() \
|
||||
ETS_INTR_ENABLE(ETS_SLC_INUM)
|
||||
|
||||
#define ETS_SLC_INTR_DISABLE() \
|
||||
ETS_INTR_DISABLE(ETS_SLC_INUM)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifndef MAC2STR
|
||||
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
|
||||
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
|
||||
#endif
|
||||
|
||||
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
|
||||
|
||||
#ifdef ESP_PLATFORM
|
||||
// Remove in IDF v6.0 (IDF-7044)
|
||||
typedef enum {
|
||||
OK = 0,
|
||||
FAIL,
|
||||
PENDING,
|
||||
BUSY,
|
||||
CANCEL,
|
||||
} STATUS __attribute__((deprecated("Use ETS_STATUS instead")));
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
222
components/esp_rom/esp32/include/esp32/rom/gpio.h
Normal file
222
components/esp_rom/esp32/include/esp32/rom/gpio.h
Normal file
@@ -0,0 +1,222 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/gpio_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup gpio_apis, uart configuration and communication related apis
|
||||
* @brief gpio apis
|
||||
*/
|
||||
|
||||
/** @addtogroup gpio_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
|
||||
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
|
||||
#define GPIO_ID_PIN0 0
|
||||
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
|
||||
#define GPIO_PIN_ADDR(i) (GPIO_PIN0_REG + i*4)
|
||||
|
||||
#define GPIO_FUNC_IN_HIGH 0x38
|
||||
#define GPIO_FUNC_IN_LOW 0x30
|
||||
|
||||
#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
|
||||
((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
|
||||
|
||||
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
|
||||
|
||||
typedef enum {
|
||||
GPIO_PIN_INTR_DISABLE = 0,
|
||||
GPIO_PIN_INTR_POSEDGE = 1,
|
||||
GPIO_PIN_INTR_NEGEDGE = 2,
|
||||
GPIO_PIN_INTR_ANYEDGE = 3,
|
||||
GPIO_PIN_INTR_LOLEVEL = 4,
|
||||
GPIO_PIN_INTR_HILEVEL = 5
|
||||
} GPIO_INT_TYPE;
|
||||
|
||||
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
|
||||
((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
|
||||
gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
|
||||
#define GPIO_DIS_OUTPUT(gpio_no) ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<(gpio_no - 32)))
|
||||
#define GPIO_INPUT_GET(gpio_no) ((gpio_no < 32) ? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
|
||||
|
||||
/**
|
||||
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
|
||||
* There is no particular ordering guaranteed; so if the order of writes is significant,
|
||||
* calling code should divide a single call into multiple calls.
|
||||
*
|
||||
* @param uint32_t set_mask : the gpios that need high level.
|
||||
*
|
||||
* @param uint32_t clear_mask : the gpios that need low level.
|
||||
*
|
||||
* @param uint32_t enable_mask : the gpios that need be changed.
|
||||
*
|
||||
* @param uint32_t disable_mask : the gpios that need disable output.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
|
||||
|
||||
/**
|
||||
* @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
|
||||
* There is no particular ordering guaranteed; so if the order of writes is significant,
|
||||
* calling code should divide a single call into multiple calls.
|
||||
*
|
||||
* @param uint32_t set_mask : the gpios that need high level.
|
||||
*
|
||||
* @param uint32_t clear_mask : the gpios that need low level.
|
||||
*
|
||||
* @param uint32_t enable_mask : the gpios that need be changed.
|
||||
*
|
||||
* @param uint32_t disable_mask : the gpios that need disable output.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
|
||||
|
||||
/**
|
||||
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
|
||||
*/
|
||||
uint32_t gpio_input_get(void);
|
||||
|
||||
/**
|
||||
* @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
|
||||
*/
|
||||
uint32_t gpio_input_get_high(void);
|
||||
|
||||
/**
|
||||
* @brief Set GPIO to wakeup the ESP32.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t i: gpio number.
|
||||
*
|
||||
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
|
||||
|
||||
/**
|
||||
* @brief disable GPIOs to wakeup the ESP32.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pin_wakeup_disable(void);
|
||||
|
||||
/**
|
||||
* @brief set gpio input to a signal, one gpio can input to several signals.
|
||||
*
|
||||
* @param uint32_t gpio : gpio number, 0~0x27
|
||||
* gpio == 0x30, input 0 to signal
|
||||
* gpio == 0x34, ???
|
||||
* gpio == 0x38, input 1 to signal
|
||||
*
|
||||
* @param uint32_t signal_idx : signal index.
|
||||
*
|
||||
* @param bool inv : the signal is inv or not
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
|
||||
|
||||
/**
|
||||
* @brief set signal output to gpio, one signal can output to several gpios.
|
||||
*
|
||||
* @param uint32_t gpio : gpio number, 0~0x27
|
||||
*
|
||||
* @param uint32_t signal_idx : signal index.
|
||||
* signal_idx == 0x100, cancel output put to the gpio
|
||||
*
|
||||
* @param bool out_inv : the signal output is inv or not
|
||||
*
|
||||
* @param bool oen_inv : the signal output enable is inv or not
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
|
||||
|
||||
/**
|
||||
* @brief Select pad as a gpio function from IOMUX.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x27
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_select_gpio(uint8_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Set pad driver capability.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x27
|
||||
*
|
||||
* @param uint8_t drv : 0-3
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
|
||||
|
||||
/**
|
||||
* @brief Pull up the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x27
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_pullup(uint8_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Pull down the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x27
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_pulldown(uint8_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Unhold the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x27
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_unhold(uint8_t gpio_num);
|
||||
|
||||
/**
|
||||
* @brief Hold the pad from gpio number.
|
||||
*
|
||||
* @param uint32_t gpio_num : gpio number, 0~0x27
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void gpio_pad_hold(uint8_t gpio_num);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
82
components/esp_rom/esp32/include/esp32/rom/libc_stubs.h
Normal file
82
components/esp_rom/esp32/include/esp32/rom/libc_stubs.h
Normal file
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _ROM_LIBC_STUBS_H_
|
||||
#define _ROM_LIBC_STUBS_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <time.h>
|
||||
#include <reent.h>
|
||||
#include <errno.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
ESP32 ROM code contains implementations of some of C library functions.
|
||||
Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
|
||||
implementation defined in the following struct.
|
||||
|
||||
The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and
|
||||
`syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU)
|
||||
and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script.
|
||||
|
||||
So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
|
||||
application must allocate syscall table structure for each CPU being used, and populate it with pointers
|
||||
to actual implementations of corresponding syscalls.
|
||||
*/
|
||||
|
||||
struct syscall_stub_table
|
||||
{
|
||||
struct _reent* (*__getreent)(void);
|
||||
void* (*_malloc_r)(struct _reent *r, size_t);
|
||||
void (*_free_r)(struct _reent *r, void*);
|
||||
void* (*_realloc_r)(struct _reent *r, void*, size_t);
|
||||
void* (*_calloc_r)(struct _reent *r, size_t, size_t);
|
||||
void (*_abort)(void);
|
||||
int (*_system_r)(struct _reent *r, const char*);
|
||||
int (*_rename_r)(struct _reent *r, const char*, const char*);
|
||||
clock_t (*_times_r)(struct _reent *r, struct tms *);
|
||||
int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
|
||||
void (*_raise_r)(struct _reent *r); /* function signature is incorrect in ROM */
|
||||
int (*_unlink_r)(struct _reent *r, const char*);
|
||||
int (*_link_r)(struct _reent *r, const char*, const char*);
|
||||
int (*_stat_r)(struct _reent *r, const char*, struct stat *);
|
||||
int (*_fstat_r)(struct _reent *r, int, struct stat *);
|
||||
void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
|
||||
int (*_getpid_r)(struct _reent *r);
|
||||
int (*_kill_r)(struct _reent *r, int, int);
|
||||
void (*_exit_r)(struct _reent *r, int);
|
||||
int (*_close_r)(struct _reent *r, int);
|
||||
int (*_open_r)(struct _reent *r, const char *, int, int);
|
||||
int (*_write_r)(struct _reent *r, int, const void *, int);
|
||||
int (*_lseek_r)(struct _reent *r, int, int, int);
|
||||
int (*_read_r)(struct _reent *r, int, void *, int);
|
||||
void (*_lock_init)(_lock_t *lock);
|
||||
void (*_lock_init_recursive)(_lock_t *lock);
|
||||
void (*_lock_close)(_lock_t *lock);
|
||||
void (*_lock_close_recursive)(_lock_t *lock);
|
||||
void (*_lock_acquire)(_lock_t *lock);
|
||||
void (*_lock_acquire_recursive)(_lock_t *lock);
|
||||
int (*_lock_try_acquire)(_lock_t *lock);
|
||||
int (*_lock_try_acquire_recursive)(_lock_t *lock);
|
||||
void (*_lock_release)(_lock_t *lock);
|
||||
void (*_lock_release_recursive)(_lock_t *lock);
|
||||
int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap);
|
||||
int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
|
||||
};
|
||||
|
||||
extern struct syscall_stub_table* syscall_table_ptr_pro;
|
||||
extern struct syscall_stub_table* syscall_table_ptr_app;
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_LIBC_STUBS_H_ */
|
||||
143
components/esp_rom/esp32/include/esp32/rom/lldesc.h
Normal file
143
components/esp_rom/esp32/include/esp32/rom/lldesc.h
Normal file
@@ -0,0 +1,143 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_LLDESC_H_
|
||||
#define _ROM_LLDESC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "sys/queue.h"
|
||||
#include "esp_rom_lldesc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define LLDESC_TX_MBLK_SIZE 268 /* */
|
||||
#define LLDESC_RX_SMBLK_SIZE 64 /* small block size, for small mgmt frame */
|
||||
#define LLDESC_RX_MBLK_SIZE 524 /* rx is large sinec we want to contain mgmt frame in one block*/
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE 64 /* it is a small buffer which is a cycle link*/
|
||||
#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE 256 /*for ampdu entry*/
|
||||
#ifdef ESP_MAC_5
|
||||
#define LLDESC_TX_MBLK_NUM 116 /* 64K / 256 */
|
||||
#define LLDESC_RX_MBLK_NUM 82 /* 64K / 512 MAX 172*/
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
|
||||
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 12
|
||||
#else
|
||||
#ifdef SBUF_RXTX
|
||||
#define LLDESC_TX_MBLK_NUM_MAX (2 * 48) /* 23K / 260 - 8 */
|
||||
#define LLDESC_RX_MBLK_NUM_MAX (2 * 48) /* 23K / 524 */
|
||||
#define LLDESC_TX_MBLK_NUM_MIN (2 * 16) /* 23K / 260 - 8 */
|
||||
#define LLDESC_RX_MBLK_NUM_MIN (2 * 16) /* 23K / 524 */
|
||||
#endif
|
||||
#define LLDESC_TX_MBLK_NUM 10 //(2 * 32) /* 23K / 260 - 8 */
|
||||
|
||||
#ifdef IEEE80211_RX_AMPDU
|
||||
#define LLDESC_RX_MBLK_NUM 30
|
||||
#else
|
||||
#define LLDESC_RX_MBLK_NUM 10
|
||||
#endif /*IEEE80211_RX_AMPDU*/
|
||||
|
||||
#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM 4
|
||||
#define LLDESC_RX_AMPDU_LEN_MLBK_NUM 8
|
||||
#endif /* !ESP_MAC_5 */
|
||||
|
||||
typedef struct tx_ampdu_entry_s{
|
||||
uint32_t sub_len :12,
|
||||
dili_num : 7,
|
||||
: 1,
|
||||
null_byte: 2,
|
||||
data : 1,
|
||||
enc : 1,
|
||||
seq : 8;
|
||||
} tx_ampdu_entry_t;
|
||||
|
||||
typedef struct lldesc_chain_s {
|
||||
lldesc_t *head;
|
||||
lldesc_t *tail;
|
||||
} lldesc_chain_t;
|
||||
|
||||
#ifdef SBUF_RXTX
|
||||
enum sbuf_mask_s {
|
||||
SBUF_MOVE_NO = 0,
|
||||
SBUF_MOVE_TX2RX,
|
||||
SBUF_MOVE_RX2TX,
|
||||
} ;
|
||||
|
||||
#define SBUF_MOVE_STEP 8
|
||||
#endif
|
||||
#define LLDESC_SIZE sizeof(struct lldesc_s)
|
||||
|
||||
/* SLC Descriptor */
|
||||
#define LLDESC_OWNER_MASK 0x80000000
|
||||
#define LLDESC_OWNER_SHIFT 31
|
||||
#define LLDESC_SW_OWNED 0
|
||||
#define LLDESC_HW_OWNED 1
|
||||
|
||||
#define LLDESC_EOF_MASK 0x40000000
|
||||
#define LLDESC_EOF_SHIFT 30
|
||||
|
||||
#define LLDESC_SOSF_MASK 0x20000000
|
||||
#define LLDESC_SOSF_SHIFT 29
|
||||
|
||||
#define LLDESC_LENGTH_MASK 0x00fff000
|
||||
#define LLDESC_LENGTH_SHIFT 12
|
||||
|
||||
#define LLDESC_SIZE_MASK 0x00000fff
|
||||
#define LLDESC_SIZE_SHIFT 0
|
||||
|
||||
#define LLDESC_ADDR_MASK 0x000fffff
|
||||
|
||||
void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t * mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
|
||||
lldesc_t **head,
|
||||
#ifdef TO_HOST_RESTART
|
||||
lldesc_t ** one_before_tail,
|
||||
#endif
|
||||
lldesc_t **tail);
|
||||
|
||||
lldesc_t *lldesc_num2link(lldesc_t * head, uint16_t nblks);
|
||||
|
||||
lldesc_t *lldesc_set_owner(lldesc_t * head, uint16_t nblks, uint8_t owner);
|
||||
|
||||
static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
|
||||
{
|
||||
lldesc_t *ds = head;
|
||||
uint32_t len = 0;
|
||||
|
||||
while (ds) {
|
||||
len += ds->length;
|
||||
ds = STAILQ_NEXT(ds, qe);
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
|
||||
{
|
||||
ds->owner = owner;
|
||||
ds->eof = eof;
|
||||
ds->sosf = sosf;
|
||||
ds->length = len;
|
||||
}
|
||||
|
||||
#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len) do { \
|
||||
(_desc)->owner = (_owner); \
|
||||
(_desc)->eof = (_eof); \
|
||||
(_desc)->sosf = (_sosf); \
|
||||
(_desc)->length = (_len); \
|
||||
} while(0)
|
||||
|
||||
#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
|
||||
|
||||
#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
|
||||
|
||||
#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_LLDESC_H_ */
|
||||
43
components/esp_rom/esp32/include/esp32/rom/md5_hash.h
Normal file
43
components/esp_rom/esp32/include/esp32/rom/md5_hash.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2003-2005, Jouni Malinen <j@w1.fi>
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*
|
||||
* MD5 internal definitions
|
||||
* Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of BSD
|
||||
* license.
|
||||
*
|
||||
* See README and COPYING for more details.
|
||||
*/
|
||||
|
||||
#ifndef _ROM_MD5_HASH_H_
|
||||
#define _ROM_MD5_HASH_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct MD5Context {
|
||||
uint32_t buf[4];
|
||||
uint32_t bits[2];
|
||||
uint8_t in[64];
|
||||
};
|
||||
|
||||
void MD5Init(struct MD5Context *context);
|
||||
void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
|
||||
void MD5Final(unsigned char digest[16], struct MD5Context *context);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_MD5_HASH_H_ */
|
||||
42
components/esp_rom/esp32/include/esp32/rom/rsa_pss.h
Normal file
42
components/esp_rom/esp32/include/esp32/rom/rsa_pss.h
Normal file
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "sdkconfig.h"
|
||||
#if CONFIG_ESP32_REV_MIN_FULL >= 300
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ETS_SIG_LEN 384 /* Bytes */
|
||||
#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
|
||||
|
||||
/* Secure Boot Version 2 - Public Key format */
|
||||
typedef struct {
|
||||
uint8_t n[384]; /* Public key modulus */
|
||||
uint32_t e; /* Public key exponent */
|
||||
uint8_t rinv[384];
|
||||
uint32_t mdash;
|
||||
} ets_rsa_pubkey_t;
|
||||
|
||||
|
||||
bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest);
|
||||
|
||||
void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask);
|
||||
|
||||
bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash, uint8_t *verified_digest);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CONFIG_ESP32_REV_MIN_FULL >= 300
|
||||
240
components/esp_rom/esp32/include/esp32/rom/rtc.h
Normal file
240
components/esp_rom/esp32/include/esp32/rom/rtc.h
Normal file
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "ets_sys.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/reset_reasons.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup rtc_apis, rtc registers and memory related apis
|
||||
* @brief rtc apis
|
||||
*/
|
||||
|
||||
/** @addtogroup rtc_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**************************************************************************************
|
||||
* Note: *
|
||||
* Some Rtc memory and registers are used, in ROM or in internal library. *
|
||||
* Please do not use reserved or used rtc memory or registers. *
|
||||
* *
|
||||
*************************************************************************************
|
||||
* RTC Memory & Store Register usage
|
||||
*************************************************************************************
|
||||
* rtc memory addr type size usage
|
||||
* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
|
||||
* 0x3ff61000+SIZE_CP Slow 8192-SIZE_CP
|
||||
*
|
||||
* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
|
||||
*
|
||||
*************************************************************************************
|
||||
* RTC store registers usage
|
||||
* RTC_CNTL_STORE0_REG Reserved
|
||||
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
|
||||
* RTC_CNTL_STORE2_REG Boot time, low word
|
||||
* RTC_CNTL_STORE3_REG Boot time, high word
|
||||
* RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
|
||||
* RTC_CNTL_STORE5_REG APB bus frequency
|
||||
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
|
||||
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
|
||||
*************************************************************************************
|
||||
*/
|
||||
|
||||
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
|
||||
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
|
||||
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
|
||||
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
|
||||
#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
|
||||
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
|
||||
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
|
||||
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
|
||||
|
||||
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
|
||||
|
||||
typedef enum {
|
||||
AWAKE = 0, //<CPU ON
|
||||
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
|
||||
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
|
||||
} SLEEP_MODE;
|
||||
|
||||
typedef enum {
|
||||
NO_MEAN = 0,
|
||||
POWERON_RESET = 1, /**<1, Vbat power on reset*/
|
||||
SW_RESET = 3, /**<3, Software reset digital core*/
|
||||
OWDT_RESET = 4, /**<4, Legacy watch dog reset digital core*/
|
||||
DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
|
||||
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
|
||||
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
|
||||
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
|
||||
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
|
||||
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
|
||||
TGWDT_CPU_RESET = 11, /**<11, Time Group reset CPU*/
|
||||
SW_CPU_RESET = 12, /**<12, Software reset CPU*/
|
||||
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
|
||||
EXT_CPU_RESET = 14, /**<14, for APP CPU, reset by PRO CPU*/
|
||||
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
|
||||
RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
|
||||
} RESET_REASON;
|
||||
|
||||
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_RESET == RESET_REASON_CORE_SW, "SW_RESET != RESET_REASON_CORE_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)TGWDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TGWDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
|
||||
|
||||
typedef enum {
|
||||
NO_SLEEP = 0,
|
||||
EXT_EVENT0_TRIG = BIT0,
|
||||
EXT_EVENT1_TRIG = BIT1,
|
||||
GPIO_TRIG = BIT2,
|
||||
TIMER_EXPIRE = BIT3,
|
||||
SDIO_TRIG = BIT4,
|
||||
MAC_TRIG = BIT5,
|
||||
UART0_TRIG = BIT6,
|
||||
UART1_TRIG = BIT7,
|
||||
TOUCH_TRIG = BIT8,
|
||||
SAR_TRIG = BIT9,
|
||||
BT_TRIG = BIT10
|
||||
} WAKEUP_REASON;
|
||||
|
||||
typedef enum {
|
||||
DISEN_WAKEUP = NO_SLEEP,
|
||||
EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
|
||||
EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
|
||||
GPIO_TRIG_EN = GPIO_TRIG,
|
||||
TIMER_EXPIRE_EN = TIMER_EXPIRE,
|
||||
SDIO_TRIG_EN = SDIO_TRIG,
|
||||
MAC_TRIG_EN = MAC_TRIG,
|
||||
UART0_TRIG_EN = UART0_TRIG,
|
||||
UART1_TRIG_EN = UART1_TRIG,
|
||||
TOUCH_TRIG_EN = TOUCH_TRIG,
|
||||
SAR_TRIG_EN = SAR_TRIG,
|
||||
BT_TRIG_EN = BT_TRIG
|
||||
} WAKEUP_ENABLE;
|
||||
|
||||
typedef enum {
|
||||
NO_INT = 0,
|
||||
WAKEUP_INT = BIT0,
|
||||
REJECT_INT = BIT1,
|
||||
SDIO_IDLE_INT = BIT2,
|
||||
RTC_WDT_INT = BIT3,
|
||||
RTC_TIME_VALID_INT = BIT4
|
||||
} RTC_INT_REASON;
|
||||
|
||||
typedef enum {
|
||||
DISEN_INT = 0,
|
||||
WAKEUP_INT_EN = WAKEUP_INT,
|
||||
REJECT_INT_EN = REJECT_INT,
|
||||
SDIO_IDLE_INT_EN = SDIO_IDLE_INT,
|
||||
RTC_WDT_INT_EN = RTC_WDT_INT,
|
||||
RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
|
||||
} RTC_INT_EN;
|
||||
|
||||
/**
|
||||
* @brief Get the reset reason for CPU.
|
||||
*
|
||||
* @param int cpu_no : CPU no.
|
||||
*
|
||||
* @return RESET_REASON
|
||||
*/
|
||||
RESET_REASON rtc_get_reset_reason(int cpu_no);
|
||||
|
||||
/**
|
||||
* @brief Get the wakeup cause for CPU.
|
||||
*
|
||||
* @param int cpu_no : CPU no.
|
||||
*
|
||||
* @return WAKEUP_REASON
|
||||
*/
|
||||
WAKEUP_REASON rtc_get_wakeup_cause(void);
|
||||
|
||||
/**
|
||||
* @brief Get CRC for Fast RTC Memory.
|
||||
*
|
||||
* @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
|
||||
*
|
||||
* @param uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
|
||||
*
|
||||
* @return uint32_t : CRC32 result
|
||||
*/
|
||||
uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
|
||||
|
||||
/**
|
||||
* @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void set_rtc_memory_crc(void);
|
||||
|
||||
/**
|
||||
* @brief Suppress ROM log by setting specific RTC control register.
|
||||
* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void rtc_suppress_rom_log(void)
|
||||
{
|
||||
/* To disable logging in the ROM, only the least significant bit of the register is used,
|
||||
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
|
||||
* you need to write to this register in the same format.
|
||||
* Namely, the upper 16 bits and lower should be the same.
|
||||
*/
|
||||
REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void __attribute__((__noreturn__)) software_reset(void);
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void software_reset_cpu(int cpu_no);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
122
components/esp_rom/esp32/include/esp32/rom/secure_boot.h
Normal file
122
components/esp_rom/esp32/include/esp32/rom/secure_boot.h
Normal file
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "ets_sys.h"
|
||||
#include "esp_assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void ets_secure_boot_start(void);
|
||||
|
||||
void ets_secure_boot_finish(void);
|
||||
|
||||
void ets_secure_boot_hash(const uint32_t *buf);
|
||||
|
||||
void ets_secure_boot_obtain(void);
|
||||
|
||||
int ets_secure_boot_check(uint32_t *buf);
|
||||
|
||||
void ets_secure_boot_rd_iv(uint32_t *buf);
|
||||
|
||||
void ets_secure_boot_rd_abstract(uint32_t *buf);
|
||||
|
||||
bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
|
||||
|
||||
int ets_secure_boot_check_finish(uint32_t *abstract);
|
||||
|
||||
#if CONFIG_ESP32_REV_MIN_FULL >= 300
|
||||
#include "rsa_pss.h"
|
||||
|
||||
#define SECURE_BOOT_NUM_BLOCKS 1
|
||||
|
||||
#define CRC_SIGN_BLOCK_LEN 1196
|
||||
#define SIG_BLOCK_PADDING 4096
|
||||
#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
|
||||
|
||||
// Anti-FI measure: use full words for success/fail internally, instead of 0/non-zero
|
||||
typedef enum {
|
||||
SBV2_SUCCESS = 0x3A5A5AA5,
|
||||
SB_SUCCESS = 0x3A5A5AA5,
|
||||
SBV2_FAILED = 0xA533885A,
|
||||
SB_FAILED = 0xA533885A,
|
||||
} secure_boot_v2_status_t;
|
||||
|
||||
/* Secure Boot Version 2 signature format for ESP32 ECO3 */
|
||||
typedef struct {
|
||||
uint8_t magic_byte;
|
||||
uint8_t version;
|
||||
uint8_t _reserved1;
|
||||
uint8_t _reserved2;
|
||||
uint8_t image_digest[32];
|
||||
ets_rsa_pubkey_t key;
|
||||
uint8_t signature[384];
|
||||
uint32_t block_crc;
|
||||
uint8_t _padding[16];
|
||||
} ets_secure_boot_sig_block_t;
|
||||
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size");
|
||||
|
||||
/* ROM supports up to 3, but IDF only checks the first one (SECURE_BOOT_NUM_BLOCKS) */
|
||||
#define SECURE_BOOT_MAX_APPENDED_SIGN_BLOCKS_TO_IMAGE 3
|
||||
|
||||
/* Multiple key block support */
|
||||
typedef struct {
|
||||
ets_secure_boot_sig_block_t block[SECURE_BOOT_MAX_APPENDED_SIGN_BLOCKS_TO_IMAGE];
|
||||
uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_MAX_APPENDED_SIGN_BLOCKS_TO_IMAGE)];
|
||||
} ets_secure_boot_signature_t;
|
||||
|
||||
ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size");
|
||||
|
||||
typedef struct {
|
||||
const void *key_digests[SECURE_BOOT_NUM_BLOCKS];
|
||||
} ets_secure_boot_key_digests_t;
|
||||
|
||||
/** @brief Verifies the signature block appended to a firmware image. Implemented in the ROM.
|
||||
*
|
||||
* This function is used to verify the bootloader before burning its public key hash into Efuse.
|
||||
* Also, it is used to verify the app on loading the image on boot and on OTA.
|
||||
*
|
||||
* @param sig The signature block flashed aligned 4096 bytes from the firmware. (ROM implementation expects 3 blocks, sig->block[3]).
|
||||
* @param image_digest The SHA-256 Digest of the firmware to be verified
|
||||
* @param trusted_key_digest The SHA-256 Digest of the public key (ets_rsa_pubkey_t) of a single signature block.
|
||||
* @param verified_digest RSA-PSS signature of image_digest. Pass an uninitialised array.
|
||||
*
|
||||
* @return SBV2_SUCCESS if signature is valid
|
||||
* SBV2_FAILED for failures.
|
||||
*/
|
||||
secure_boot_v2_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const uint8_t *trusted_key_digest, uint8_t *verified_digest);
|
||||
|
||||
/** @brief This function verifies the 1st stage bootloader. Implemented in the ROM.
|
||||
* Reboots post verification. It reads the Efuse key for verification of the public key.
|
||||
*
|
||||
* This function is not used in the current workflow.
|
||||
*
|
||||
*/
|
||||
void ets_secure_boot_verify_boot_bootloader(void);
|
||||
|
||||
/** @brief Confirms if the secure boot V2 has been enabled. Implemented in the ROM.
|
||||
*
|
||||
* In ESP32-ECO3 - It checks the value of ABS_DONE_1 in EFuse.
|
||||
*
|
||||
* @return true if is Secure boot v2 has been enabled
|
||||
* False if Secure boot v2 has not been enabled.
|
||||
*/
|
||||
bool ets_use_secure_boot_v2(void);
|
||||
|
||||
#else
|
||||
#define SECURE_BOOT_NUM_BLOCKS 0
|
||||
|
||||
#endif /* CONFIG_ESP32_REV_MIN_FULL >= 300 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
57
components/esp_rom/esp32/include/esp32/rom/sha.h
Normal file
57
components/esp_rom/esp32/include/esp32/rom/sha.h
Normal file
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
ROM functions for hardware SHA support.
|
||||
|
||||
It is not recommended to use these functions directly. If using
|
||||
them from esp-idf then use the esp_sha_lock_engine() and
|
||||
esp_sha_lock_memory_block() functions in esp32/sha.h to ensure
|
||||
exclusive access.
|
||||
*/
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _ROM_SHA_H_
|
||||
#define _ROM_SHA_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct SHAContext {
|
||||
bool start;
|
||||
uint32_t total_input_bits[4];
|
||||
} SHA_CTX;
|
||||
|
||||
enum SHA_TYPE {
|
||||
SHA1 = 0,
|
||||
SHA2_256,
|
||||
SHA2_384,
|
||||
SHA2_512,
|
||||
|
||||
|
||||
SHA_INVALID = -1,
|
||||
};
|
||||
|
||||
/* Do not use these function in multi core mode due to
|
||||
* inside they have no safe implementation (without DPORT workaround).
|
||||
*/
|
||||
void ets_sha_init(SHA_CTX *ctx);
|
||||
|
||||
void ets_sha_enable(void);
|
||||
|
||||
void ets_sha_disable(void);
|
||||
|
||||
void ets_sha_update(SHA_CTX *ctx, enum SHA_TYPE type, const uint8_t *input, size_t input_bits);
|
||||
|
||||
void ets_sha_finish(SHA_CTX *ctx, enum SHA_TYPE type, uint8_t *output);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_SHA_H_ */
|
||||
454
components/esp_rom/esp32/include/esp32/rom/spi_flash.h
Normal file
454
components/esp_rom/esp32/include/esp32/rom/spi_flash.h
Normal file
@@ -0,0 +1,454 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "esp_attr.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_spiflash.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*************************************************************
|
||||
* Note
|
||||
*************************************************************
|
||||
* 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
|
||||
* used as an SPI master to access Flash and ext-SRAM by
|
||||
* Cache module. It will support Decryto read for Flash,
|
||||
* read/write for ext-SRAM. And SPI1 is also used as an
|
||||
* SPI master for Flash read/write and ext-SRAM read/write.
|
||||
* It will support Encrypto write for Flash.
|
||||
* 2. As an SPI master, SPI support Highest clock to 80M,
|
||||
* however, Flash with 80M Clock should be configured
|
||||
* for different Flash chips. If you want to use 80M
|
||||
* clock We should use the SPI that is certified by
|
||||
* Espressif. However, the certification is not started
|
||||
* at the time, so please use 40M clock at the moment.
|
||||
* 3. SPI Flash can use 2 lines or 4 lines mode. If you
|
||||
* use 2 lines mode, you can save two pad SPIHD and
|
||||
* SPIWP for gpio. ESP32 support configured SPI pad for
|
||||
* Flash, the configuration is stored in efuse and flash.
|
||||
* However, the configurations of pads should be certified
|
||||
* by Espressif. If you use this function, please use 40M
|
||||
* clock at the moment.
|
||||
* 4. ESP32 support to use Common SPI command to configure
|
||||
* Flash to QIO mode, if you failed to configure with fix
|
||||
* command. With Common SPI Command, ESP32 can also provide
|
||||
* a way to use same Common SPI command groups on different
|
||||
* Flash chips.
|
||||
* 5. This functions are not protected by packeting, Please use the
|
||||
*************************************************************
|
||||
*/
|
||||
|
||||
#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1)
|
||||
#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1)
|
||||
|
||||
#define SPI0_R_QIO_DUMMY_CYCLELEN 3
|
||||
#define SPI0_R_QIO_ADDR_BITSLEN 31
|
||||
#define SPI0_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI0_R_DIO_DUMMY_CYCLELEN 1
|
||||
#define SPI0_R_DIO_ADDR_BITSLEN 27
|
||||
#define SPI0_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI0_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define SPI1_R_QIO_DUMMY_CYCLELEN 3
|
||||
#define SPI1_R_QIO_ADDR_BITSLEN 31
|
||||
#define SPI1_R_FAST_DUMMY_CYCLELEN 7
|
||||
#define SPI1_R_DIO_DUMMY_CYCLELEN 3
|
||||
#define SPI1_R_DIO_ADDR_BITSLEN 31
|
||||
#define SPI1_R_FAST_ADDR_BITSLEN 23
|
||||
#define SPI1_R_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23
|
||||
|
||||
#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B
|
||||
|
||||
//SPI address register
|
||||
#define ESP_ROM_SPIFLASH_BYTES_LEN 24
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64
|
||||
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f
|
||||
|
||||
//Extra dummy for flash read
|
||||
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
|
||||
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M 0
|
||||
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
|
||||
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2
|
||||
|
||||
typedef struct {
|
||||
uint8_t data_length;
|
||||
uint8_t read_cmd0;
|
||||
uint8_t read_cmd1;
|
||||
uint8_t write_cmd;
|
||||
uint16_t data_mask;
|
||||
uint16_t data;
|
||||
} esp_rom_spiflash_common_cmd_t;
|
||||
|
||||
/**
|
||||
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
|
||||
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
|
||||
*
|
||||
* @param uint8_t legacy: always keeping false.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
|
||||
|
||||
/**
|
||||
* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t *status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
|
||||
|
||||
/**
|
||||
* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t *status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
|
||||
|
||||
/**
|
||||
* @brief Write status to Flash status register.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t status_value : Value to .
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
|
||||
|
||||
/**
|
||||
* @brief Use a command to Read Flash status register.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @param uint32_t*status : The pointer to which to return the Flash status value.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
|
||||
|
||||
/**
|
||||
* @brief Config SPI Flash read mode when init.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
|
||||
*
|
||||
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
|
||||
|
||||
/**
|
||||
* @brief Config SPI Flash clock divisor.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t freqdiv: clock divisor.
|
||||
*
|
||||
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
|
||||
|
||||
/**
|
||||
* @brief Clear all SR bits except QE bit.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
|
||||
|
||||
/**
|
||||
* @brief Clear all SR bits except QE bit.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
|
||||
|
||||
/**
|
||||
* @brief SPI flash set BP0 to BP2.(Only valid when WRSR+2Bytes)
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
|
||||
|
||||
/**
|
||||
* @brief Update SPI Flash parameter.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
|
||||
*
|
||||
* @param uint32_t chip_size : The Flash size.
|
||||
*
|
||||
* @param uint32_t block_size : The Flash block size.
|
||||
*
|
||||
* @param uint32_t sector_size : The Flash sector size.
|
||||
*
|
||||
* @param uint32_t page_size : The Flash page size.
|
||||
*
|
||||
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
|
||||
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
|
||||
|
||||
/**
|
||||
* @brief Erase whole flash chip.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
|
||||
|
||||
/**
|
||||
* @brief Erase a 64KB block of flash
|
||||
* Uses SPI flash command D8H.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t block_num : Which block to erase.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
|
||||
|
||||
/**
|
||||
* @brief Erase a sector of flash.
|
||||
* Uses SPI flash command 20H.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t sector_num : Which sector to erase.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
|
||||
|
||||
/**
|
||||
* @brief Erase some sectors.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
|
||||
*
|
||||
* @param uint32_t area_len : Length to erase, should be sector aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
|
||||
|
||||
/**
|
||||
* @brief Write Data to Flash, you should Erase it yourself if need.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
|
||||
*
|
||||
* @param const uint32_t *src : The pointer to data which is to write.
|
||||
*
|
||||
* @param uint32_t len : Length to write, should be 4 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
|
||||
|
||||
/**
|
||||
* @brief Read Data from Flash, you should Erase it yourself if need.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
|
||||
*
|
||||
* @param uint32_t *dest : The buf to read the data.
|
||||
*
|
||||
* @param uint32_t len : Length to read, should be 4 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
|
||||
|
||||
/**
|
||||
* @brief SPI1 go into encrypto mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_write_encrypted_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
|
||||
*
|
||||
* @param uint32_t *data : The pointer to data which is to write.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data);
|
||||
|
||||
/**
|
||||
* @brief SPI1 go out of encrypto mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void esp_rom_spiflash_write_encrypted_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Write data to flash with transparent encryption.
|
||||
* @note Sectors to be written should already be erased.
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint32_t flash_addr : Address to write, should be 32 byte aligned.
|
||||
*
|
||||
* @param uint32_t *data : The pointer to data to write. Note, this pointer must
|
||||
* be 32 bit aligned and the content of the data will be
|
||||
* modified by the encryption function.
|
||||
*
|
||||
* @param uint32_t len : Length to write, should be 32 bytes aligned.
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
|
||||
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
|
||||
|
||||
|
||||
/** @brief Wait until SPI flash write operation is complete
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* Reads the Write In Progress bit of the SPI flash status register,
|
||||
* repeats until this bit is zero (indicating write complete).
|
||||
*
|
||||
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
|
||||
* ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
|
||||
|
||||
|
||||
/** @brief Enable Quad I/O pin functions
|
||||
*
|
||||
* @note Please do not call this function in SDK.
|
||||
*
|
||||
* Sets the HD & WP pin functions for Quad I/O modes, based on the
|
||||
* efuse SPI pin configuration.
|
||||
*
|
||||
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
|
||||
*
|
||||
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
|
||||
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
|
||||
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
|
||||
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
|
||||
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
|
||||
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
|
||||
*/
|
||||
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
|
||||
|
||||
/**
|
||||
* @brief Clear WEL bit unconditionally.
|
||||
*
|
||||
* @return always ESP_ROM_SPIFLASH_RESULT_OK
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Set WREN bit.
|
||||
*
|
||||
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
|
||||
*
|
||||
* @return always ESP_ROM_SPIFLASH_RESULT_OK
|
||||
*/
|
||||
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
19
components/esp_rom/esp32/include/esp32/rom/tbconsole.h
Normal file
19
components/esp_rom/esp32/include/esp32/rom/tbconsole.h
Normal file
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _ROM_TBCONSOLE_H_
|
||||
#define _ROM_TBCONSOLE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void start_tb_console(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_TBCONSOLE_H_ */
|
||||
99
components/esp_rom/esp32/include/esp32/rom/tjpgd.h
Normal file
99
components/esp_rom/esp32/include/esp32/rom/tjpgd.h
Normal file
@@ -0,0 +1,99 @@
|
||||
/*----------------------------------------------------------------------------/
|
||||
/ TJpgDec - Tiny JPEG Decompressor include file (C)ChaN, 2012
|
||||
/----------------------------------------------------------------------------*/
|
||||
#ifndef _TJPGDEC
|
||||
#define _TJPGDEC
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* System Configurations */
|
||||
|
||||
#define JD_SZBUF 512 /* Size of stream input buffer */
|
||||
#define JD_FORMAT 0 /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
|
||||
#define JD_USE_SCALE 1 /* Use descaling feature for output */
|
||||
#define JD_TBLCLIP 1 /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* These types must be 16-bit, 32-bit or larger integer */
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* These types must be 8-bit integer */
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
/* These types must be 16-bit integer */
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned short WCHAR;
|
||||
|
||||
/* These types must be 32-bit integer */
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef unsigned long DWORD;
|
||||
|
||||
|
||||
/* Error code */
|
||||
typedef enum {
|
||||
JDR_OK = 0, /* 0: Succeeded */
|
||||
JDR_INTR, /* 1: Interrupted by output function */
|
||||
JDR_INP, /* 2: Device error or wrong termination of input stream */
|
||||
JDR_MEM1, /* 3: Insufficient memory pool for the image */
|
||||
JDR_MEM2, /* 4: Insufficient stream input buffer */
|
||||
JDR_PAR, /* 5: Parameter error */
|
||||
JDR_FMT1, /* 6: Data format error (may be damaged data) */
|
||||
JDR_FMT2, /* 7: Right format but not supported */
|
||||
JDR_FMT3 /* 8: Not supported JPEG standard */
|
||||
} JRESULT;
|
||||
|
||||
|
||||
|
||||
/* Rectangular structure */
|
||||
typedef struct {
|
||||
WORD left, right, top, bottom;
|
||||
} JRECT;
|
||||
|
||||
|
||||
|
||||
/* Decompressor object structure */
|
||||
typedef struct JDEC JDEC;
|
||||
struct JDEC {
|
||||
UINT dctr; /* Number of bytes available in the input buffer */
|
||||
BYTE* dptr; /* Current data read ptr */
|
||||
BYTE* inbuf; /* Bit stream input buffer */
|
||||
BYTE dmsk; /* Current bit in the current read byte */
|
||||
BYTE scale; /* Output scaling ratio */
|
||||
BYTE msx, msy; /* MCU size in unit of block (width, height) */
|
||||
BYTE qtid[3]; /* Quantization table ID of each component */
|
||||
SHORT dcv[3]; /* Previous DC element of each component */
|
||||
WORD nrst; /* Restart interval */
|
||||
UINT width, height; /* Size of the input image (pixel) */
|
||||
BYTE* huffbits[2][2]; /* Huffman bit distribution tables [id][dcac] */
|
||||
WORD* huffcode[2][2]; /* Huffman code word tables [id][dcac] */
|
||||
BYTE* huffdata[2][2]; /* Huffman decoded data tables [id][dcac] */
|
||||
LONG* qttbl[4]; /* Dequaitizer tables [id] */
|
||||
void* workbuf; /* Working buffer for IDCT and RGB output */
|
||||
BYTE* mcubuf; /* Working buffer for the MCU */
|
||||
void* pool; /* Pointer to available memory pool */
|
||||
UINT sz_pool; /* Size of memory pool (bytes available) */
|
||||
UINT (*infunc)(JDEC*, BYTE*, UINT);/* Pointer to jpeg stream input function */
|
||||
void* device; /* Pointer to I/O device identifier for the session */
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* TJpgDec API functions */
|
||||
JRESULT jd_prepare (JDEC*, UINT(*)(JDEC*,BYTE*,UINT), void*, UINT, void*);
|
||||
JRESULT jd_decomp (JDEC*, UINT(*)(JDEC*,void*,JRECT*), BYTE);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _TJPGDEC */
|
||||
409
components/esp_rom/esp32/include/esp32/rom/uart.h
Normal file
409
components/esp_rom/esp32/include/esp32/rom/uart.h
Normal file
@@ -0,0 +1,409 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "esp_types.h"
|
||||
#include "esp_attr.h"
|
||||
#include "ets_sys.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/uart_periph.h"
|
||||
#include "soc/uart_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \defgroup uart_apis, uart configuration and communication related apis
|
||||
* @brief uart apis
|
||||
*/
|
||||
|
||||
/** @addtogroup uart_apis
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RX_BUFF_SIZE 0x100
|
||||
#define TX_BUFF_SIZE 100
|
||||
|
||||
//uart int enable register ctrl bits
|
||||
#define UART_RCV_INTEN BIT0
|
||||
#define UART_TRX_INTEN BIT1
|
||||
#define UART_LINE_STATUS_INTEN BIT2
|
||||
|
||||
//uart int identification ctrl bits
|
||||
#define UART_INT_FLAG_MASK 0x0E
|
||||
|
||||
//uart fifo ctrl bits
|
||||
#define UART_CLR_RCV_FIFO BIT1
|
||||
#define UART_CLR_TRX_FIFO BIT2
|
||||
#define UART_RCVFIFO_TRG_LVL_BITS BIT6
|
||||
|
||||
//uart line control bits
|
||||
#define UART_DIV_LATCH_ACCESS_BIT BIT7
|
||||
|
||||
//uart line status bits
|
||||
#define UART_RCV_DATA_RDY_FLAG BIT0
|
||||
#define UART_RCV_OVER_FLOW_FLAG BIT1
|
||||
#define UART_RCV_PARITY_ERR_FLAG BIT2
|
||||
#define UART_RCV_FRAME_ERR_FLAG BIT3
|
||||
#define UART_BRK_INT_FLAG BIT4
|
||||
#define UART_TRX_FIFO_EMPTY_FLAG BIT5
|
||||
#define UART_TRX_ALL_EMPTY_FLAG BIT6 // include fifo and shift reg
|
||||
#define UART_RCV_ERR_FLAG BIT7
|
||||
|
||||
//send and receive message frame head
|
||||
#define FRAME_FLAG 0x7E
|
||||
|
||||
typedef enum {
|
||||
UART_LINE_STATUS_INT_FLAG = 0x06,
|
||||
UART_RCV_FIFO_INT_FLAG = 0x04,
|
||||
UART_RCV_TMOUT_INT_FLAG = 0x0C,
|
||||
UART_TXBUFF_EMPTY_INT_FLAG = 0x02
|
||||
} UartIntType; //consider bit0 for int_flag
|
||||
|
||||
typedef enum {
|
||||
RCV_ONE_BYTE = 0x0,
|
||||
RCV_FOUR_BYTE = 0x1,
|
||||
RCV_EIGHT_BYTE = 0x2,
|
||||
RCV_FOURTEEN_BYTE = 0x3
|
||||
} UartRcvFifoTrgLvl;
|
||||
|
||||
typedef enum {
|
||||
FIVE_BITS = 0x0,
|
||||
SIX_BITS = 0x1,
|
||||
SEVEN_BITS = 0x2,
|
||||
EIGHT_BITS = 0x3
|
||||
} UartBitsNum4Char;
|
||||
|
||||
typedef enum {
|
||||
ONE_STOP_BIT = 1,
|
||||
ONE_HALF_STOP_BIT = 2,
|
||||
TWO_STOP_BIT = 3
|
||||
} UartStopBitsNum;
|
||||
|
||||
typedef enum {
|
||||
NONE_BITS = 0,
|
||||
ODD_BITS = 2,
|
||||
EVEN_BITS = 3
|
||||
|
||||
} UartParityMode;
|
||||
|
||||
typedef enum {
|
||||
STICK_PARITY_DIS = 0,
|
||||
STICK_PARITY_EN = 2
|
||||
} UartExistParity;
|
||||
|
||||
typedef enum {
|
||||
BIT_RATE_9600 = 9600,
|
||||
BIT_RATE_19200 = 19200,
|
||||
BIT_RATE_38400 = 38400,
|
||||
BIT_RATE_57600 = 57600,
|
||||
BIT_RATE_115200 = 115200,
|
||||
BIT_RATE_230400 = 230400,
|
||||
BIT_RATE_460800 = 460800,
|
||||
BIT_RATE_921600 = 921600
|
||||
} UartBautRate;
|
||||
|
||||
typedef enum {
|
||||
NONE_CTRL,
|
||||
HARDWARE_CTRL,
|
||||
XON_XOFF_CTRL
|
||||
} UartFlowCtrl;
|
||||
|
||||
typedef enum {
|
||||
EMPTY,
|
||||
UNDER_WRITE,
|
||||
WRITE_OVER
|
||||
} RcvMsgBuffState;
|
||||
|
||||
typedef struct {
|
||||
uint8_t *pRcvMsgBuff;
|
||||
uint8_t *pWritePos;
|
||||
uint8_t *pReadPos;
|
||||
uint8_t TrigLvl;
|
||||
RcvMsgBuffState BuffState;
|
||||
} RcvMsgBuff;
|
||||
|
||||
typedef struct {
|
||||
uint32_t TrxBuffSize;
|
||||
uint8_t *pTrxBuff;
|
||||
} TrxMsgBuff;
|
||||
|
||||
typedef enum {
|
||||
BAUD_RATE_DET,
|
||||
WAIT_SYNC_FRM,
|
||||
SRCH_MSG_HEAD,
|
||||
RCV_MSG_BODY,
|
||||
RCV_ESC_CHAR,
|
||||
} RcvMsgState;
|
||||
|
||||
typedef struct {
|
||||
UartBautRate baut_rate;
|
||||
UartBitsNum4Char data_bits;
|
||||
UartExistParity exist_parity;
|
||||
UartParityMode parity; // chip size in byte
|
||||
UartStopBitsNum stop_bits;
|
||||
UartFlowCtrl flow_ctrl;
|
||||
uint8_t buff_uart_no; //indicate which uart use tx/rx buffer
|
||||
uint8_t tx_uart_no;
|
||||
RcvMsgBuff rcv_buff;
|
||||
// TrxMsgBuff trx_buff;
|
||||
RcvMsgState rcv_state;
|
||||
int received;
|
||||
} UartDevice;
|
||||
|
||||
/**
|
||||
* @brief Init uart device struct value and reset uart0/uart1 rx.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uartAttach(void);
|
||||
|
||||
/**
|
||||
* @brief Init uart0 or uart1 for UART download booting mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, else for UART1.
|
||||
*
|
||||
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Uart_Init(uint8_t uart_no, uint32_t clock);
|
||||
|
||||
/**
|
||||
* @brief Modify uart baudrate.
|
||||
* This function will reset RX/TX fifo for uart.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
|
||||
|
||||
/**
|
||||
* @brief Init uart0 or uart1 for UART download booting mode.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
|
||||
* 1, two UART modules, hard to detect, detect and return.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
|
||||
|
||||
/**
|
||||
* @brief Switch printf channel of uart_tx_one_char.
|
||||
* Please do not call this function when printf.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uart_tx_switch(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Switch message exchange channel for UART download booting.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uart_buff_switch(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Output a char to printf channel, wait until fifo not full.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS uart_tx_one_char(uint8_t TxChar);
|
||||
|
||||
/**
|
||||
* @brief Output a char to message exchange channel, wait until fifo not full.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS uart_tx_one_char2(uint8_t TxChar);
|
||||
|
||||
/**
|
||||
* @brief Wait until uart tx full empty.
|
||||
*
|
||||
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void uart_tx_flush(uint8_t uart_no);
|
||||
|
||||
/**
|
||||
* @brief Wait until uart tx full empty and the last char send ok.
|
||||
*
|
||||
* @param uart_no : 0 for UART0, 1 for UART1, 2 for UART2
|
||||
*
|
||||
* The function defined in ROM code has a bug, so we define the correct version
|
||||
* here for compatibility.
|
||||
*/
|
||||
static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) {
|
||||
uint32_t status;
|
||||
do {
|
||||
status = READ_PERI_REG(UART_STATUS_REG(uart_no));
|
||||
/* either tx count or state is non-zero */
|
||||
} while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get an input char from message channel.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pRxChar : the pointer to store the char.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS uart_rx_one_char(uint8_t *pRxChar);
|
||||
|
||||
/**
|
||||
* @brief Get an input char from message channel, wait until successful.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return char : input char value.
|
||||
*/
|
||||
char uart_rx_one_char_block(void);
|
||||
|
||||
/**
|
||||
* @brief Get an input string line from message channel.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pString : the pointer to store the string.
|
||||
*
|
||||
* @param uint8_t MaxStrlen : the max string length, include '\0'.
|
||||
*
|
||||
* @return OK.
|
||||
*/
|
||||
ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
|
||||
|
||||
/**
|
||||
* @brief Process uart received information in the interrupt handler.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param void *para : the message receive buffer.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void uart_rx_intr_handler(void *para);
|
||||
|
||||
/**
|
||||
* @brief Get an char from receive buffer.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
|
||||
*
|
||||
* @param uint8_t *pRxByte : the pointer to store the char.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
|
||||
|
||||
/**
|
||||
* @brief Get all chars from receive buffer.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pCmdLn : the pointer to store the string.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn);
|
||||
|
||||
/**
|
||||
* @brief Get uart configuration struct.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return UartDevice * : uart configuration struct pointer.
|
||||
*/
|
||||
UartDevice *GetUartDevice(void);
|
||||
|
||||
/**
|
||||
* @brief Send an packet to download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *p : the pointer to output string.
|
||||
*
|
||||
* @param int len : the string length.
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
void send_packet(uint8_t *p, int len);
|
||||
|
||||
/**
|
||||
* @brief Receive an packet from download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *p : the pointer to input string.
|
||||
*
|
||||
* @param int len : If string length > len, the string will be truncated.
|
||||
*
|
||||
* @param uint8_t is_sync : 0, only one UART module;
|
||||
* 1, two UART modules.
|
||||
*
|
||||
* @return int : the length of the string.
|
||||
*/
|
||||
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
|
||||
|
||||
/**
|
||||
* @brief Send an packet to download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pData : the pointer to input string.
|
||||
*
|
||||
* @param uint16_t DataLen : the string length.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
|
||||
|
||||
/**
|
||||
* @brief Receive an packet from download tool, with SLIP escaping.
|
||||
* Please do not call this function in SDK.
|
||||
*
|
||||
* @param uint8_t *pData : the pointer to input string.
|
||||
*
|
||||
* @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
|
||||
*
|
||||
* @param uint8_t is_sync : 0, only one UART module;
|
||||
* 1, two UART modules.
|
||||
*
|
||||
* @return OK for successful.
|
||||
* FAIL for failed.
|
||||
*/
|
||||
ETS_STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
|
||||
|
||||
extern UartDevice UartDev;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user